View TMP89CH42UG_8551184.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8 bit microcontroller tlcs-870/c1 series tmp89ch42
? 2009 toshiba corporation all rights reserved
considerations for using both mask rom and flash products ? flash memory control registers mask rom products do not contain the flash memory control registers shown in the table below. therefore, a program that accesses these registers operates differently between mask rom and flash products. if you use a flash product to check the operation of a program written for a mask rom product, be sure not to write instructions that access these registers in the program. register name address mask rom product flash product 89cm42, 89ch42 89fm42, 89fh42 flscr1 0x0fd0 not available available flscr2 / flscrm 0x0fd1 flsstb 0x0fd2 spcr 0x0fd3 ? conversion accuracy of the ad converter the conversion accuracy of the ad converter differs between mask rom and flash products, as shown below. when developing your application system, careful consideration must be given to these accuracy differences. (v ss = 0.0 v, 4.5 v v dd 5.5 v, topr = ?40 to 85 c) parameter condition min typ. max unit non-linearity error v dd = a vdd / v aref = 5.0 v v ss = 0.0 v ? ? 89cm42 89ch42 89fm42 89fh42 lsb 4 3 zero-point error ? ? 4 3 full-scale error ? ? 4 3 total error ? ? 4 3 (v ss = 0.0 v, 2.7 v v dd < 4.5 v, topr = ?40 to 85 c) parameter condition min typ. max unit non-linearity error v dd = a vdd / v aref = 2.7 v v ss = 0.0 v ? ? 89cm42 89ch42 89fm42 89fh42 lsb 4 3 zero-point error ? ? 4 3 full-scale error ? ? 4 3 total error ? ? 4 3 (v ss = 0.0 v, 2.2 v v dd < 2.7 v, topr = ?40 to 85 c) parameter condition min typ. max unit non-linearity error v dd = a vdd / v aref = 2.2 v v ss = 0.0 v ? ? 89cm42 89ch42 89fm42 89fh42 lsb 5 4 zero-point error ? ? 5 4 full-scale error ? ? 5 4 total error ? ? 5 4 tmp89ch42
precaution for using the emulation chip (development tool) ? precaution for debugging the voltage detection circuit in debug using the rte870/c1 in-circuit emulator (ice mode) with the tmp89c900 mounted on it, no interrupt is generated when the supply voltage rises to the detection voltage. since the #!undefined!# may operate differently, take account of this difference when debugging programs. for detail, refer to the chapter of voltage detection circuit. tmp89ch42
revision history date revision 2008/2/16 1 first release 2008/9/4 2 contents revised 2009/7/16 3 contents revised

table of contents considerations for using both mask rom and flash products tmp89ch42 1.1 features ...................................................................................................................................... 1 1.2 pin assignment .......................................................................................................................... 3 1.3 block diagram ........................................................................................................................... 4 1.4 pin names and functions .......................................................................................................... 5 2. cpu core 2.1 configuration ............................................................................................................................. 9 2.2 memory space ............................................................................................................................ 9 2.2.1 code area ............................................................................................................................................................................. 9 2.2.1.1 ram 2.2.1.2 maskrom 2.2.2 data area ............................................................................................................................................................................ 12 2.2.2.1 sfr 2.2.2.2 ram 2.2.2.3 maskrom 2.3 system clock controller ........................................................................................................... 14 2.3.1 configuration ..................................................................................................................................................................... 14 2.3.2 control ............................................................................................................................................................................... 14 2.3.3 functions ............................................................................................................................................................................16 2.3.3.1 clock generator 2.3.3.2 clock gear 2.3.3.3 timing generator 2.3.4 warm-up counter ............................................................................................................................................................... 19 2.3.4.1 warm-up counter operation when the oscillation is enabled by the hardware 2.3.4.2 warm-up counter operation when the oscillation is enabled by the software 2.3.5 operation mode control circuit .......................................................................................................................................... 21 2.3.5.1 single-clock mode 2.3.5.2 dual-clock mode 2.3.5.3 stop mode 2.3.5.4 transition of operation modes 2.3.6 operation mode control .................................................................................................................................................... 26 2.3.6.1 stop mode 2.3.6.2 idle1/2 and sleep1 modes 2.3.6.3 idle0 and sleep0 modes 2.3.6.4 slow mode 2.4 reset control circuit ............................................................................................................... 37 2.4.1 configuration ..................................................................................................................................................................... 37 2.4.2 control ............................................................................................................................................................................... 37 2.4.3 functions ............................................................................................................................................................................39 2.4.4 reset signal generating factors ........................................................................................................................................ 41 2.4.4.1 power-on reset 2.4.4.2 external reset input (reset pin input) 2.4.4.3 voltage detection reset 2.4.4.4 watchdog timer reset 2.4.4.5 system clock reset 2.4.4.6 trimming data reset 2.4.4.7 internal factor reset detection status register 2.4.4.8 how to use the external reset input pin as a port i
2.5 revision history ...................................................................................................................... 45 3. interrupt control circuit 3.1 configuration ........................................................................................................................... 48 3.2 interrupt latches (il25 to il3) ................................................................................................49 3.3 interrupt enable register (eir) ............................................................................................... 50 3.3.1 interrupt master enable flag (imf) .................................................................................................................................... 50 3.3.2 individual interrupt enable flags (ef25 to ef4) ................................................................................................................ 50 3.4 maskable interrupt priority change function ......................................................................... 53 3.5 interrupt sequence ................................................................................................................... 55 3.5.1 initial setting ......................................................................................................................................................................55 3.5.2 interrupt acceptance processing ......................................................................................................................................... 55 3.5.3 saving/restoring general-purpose registers ........................................................................................................................ 56 3.5.3.1 using push and pop instructions 3.5.3.2 using data transfer instructions 3.5.3.3 using a register bank to save/restore general-purpose registers 3.5.4 interrupt return ................................................................................................................................................................... 58 3.6 software interrupt (intsw) ....................................................................................................59 3.6.1 address error detection ...................................................................................................................................................... 59 3.6.2 debugging .......................................................................................................................................................................... 59 3.7 undefined instruction interrupt (intundef) ....................................................................... 59 3.8 revision history ...................................................................................................................... 60 4. external interrupt control circuit 4.1 configuration ........................................................................................................................... 61 4.2 control ..................................................................................................................................... 61 4.3 function ................................................................................................................................... 65 4.3.1 low power consumption function ..................................................................................................................................... 66 4.3.2 external interrupt 0 ............................................................................................................................................................ 66 4.3.3 external interrupts 1/2/3 .................................................................................................................................................... 67 4.3.3.1 interrupt request signal generating condition detection function 4.3.3.2 a noise canceller pass signal monitoring function when interrupt request signals are generated 4.3.3.3 noise cancel time selection function 4.3.4 external interrupt 4 ............................................................................................................................................................ 68 4.3.4.1 interrupt request signal generating condition detection function 4.3.4.2 a noise canceller pass signal monitoring function when interrupt request signals are generated 4.3.4.3 noise cancel time selection function 4.3.5 external interrupt 5 ............................................................................................................................................................ 70 5. watchdog timer (wdt) 5.1 configuration ........................................................................................................................... 71 5.2 control ..................................................................................................................................... 72 5.3 functions ..................................................................................................................................74 5.3.1 setting of enabling/disabling the watchdog timer operation ............................................................................................. 74 5.3.2 setting the clear time of the 8-bit up counter .....................................................................................................................74 5.3.3 setting the overflow time of the 8-bit up counter .............................................................................................................. 75 5.3.4 setting an overflow detection signal of the 8-bit up counter ............................................................................................. 75 5.3.5 writing the watchdog timer control codes ......................................................................................................................... 76 5.3.6 reading the 8-bit up counter .............................................................................................................................................. 76 5.3.7 reading the watchdog timer status .................................................................................................................................... 76 ii
6. power-on reset circuit 6.1 configuration ........................................................................................................................... 79 6.2 function ................................................................................................................................... 79 7. voltage detection circuit 7.1 configuration ........................................................................................................................... 81 7.2 control ..................................................................................................................................... 82 7.3 function ................................................................................................................................... 83 7.3.1 enabling/disabling the voltage detection operation ........................................................................................................... 83 7.3.2 selecting the voltage detection operation mode ................................................................................................................ 83 7.3.3 selecting the detection voltage level ................................................................................................................................. 84 7.3.4 voltage detection flag and voltage detection status flag ................................................................................................... 84 7.4 register settings ...................................................................................................................... 86 7.4.1 setting procedure when the operation mode is set to generate intvltd interrupt request signals ................................ 86 7.4.2 setting procedure when the operation mode is set to generate voltage detection reset signals ......................................... 86 7.5 revision history ...................................................................................................................... 88 8. i/o ports 8.1 i/o port control registers ....................................................................................................... 91 8.2 list of i/o port settings ........................................................................................................... 92 8.3 i/o port registers .................................................................................................................... 95 8.3.1 port p0 (p03 to p00) .......................................................................................................................................................... 95 8.3.2 port p1 (p13 to p10) .......................................................................................................................................................... 99 8.3.3 port p2 (p27 to p20) ........................................................................................................................................................ 103 8.3.4 port p4 (p47 to p40) ........................................................................................................................................................ 107 8.3.5 port p7 (p77 to p70) ........................................................................................................................................................ 110 8.3.6 port p8 (p81 to p80) ........................................................................................................................................................ 112 8.3.7 port p9 (p91 to p90) ........................................................................................................................................................ 115 8.3.8 port pb (pb7 to pb4) ...................................................................................................................................................... 118 8.4 serial interface selecting function ........................................................................................ 121 8.5 revision history .................................................................................................................... 124 9. special function registers 9.1 sfr1 (0x0000 to 0x003f) ..................................................................................................... 125 9.2 sfr2 (0x0f00 to 0x0fff) .....................................................................................................126 9.3 sfr3 (0x0e40 to 0x0eff) .................................................................................................... 128 10. low power consumption function for peripherals 10.1 control ................................................................................................................................. 132 11. divider output ( dvo ) iii
11.1 configuration .......................................................................................................................135 11.2 control ................................................................................................................................. 136 11.3 function ............................................................................................................................... 137 11.4 revision history .................................................................................................................. 138 12. time base timer (tbt) 12.1 time base timer ................................................................................................................. 139 12.1.1 configuration ................................................................................................................................................................. 139 12.1.2 control ........................................................................................................................................................................... 139 12.1.3 functions ........................................................................................................................................................................140 12.2 revision history .................................................................................................................. 142 13. 16-bit timer counter (tca) 13.1 configuration ....................................................................................................................... 144 13.2 control ................................................................................................................................. 145 13.3 low power consumption function ..................................................................................... 150 13.4 timer function .................................................................................................................... 151 13.4.1 timer mode .................................................................................................................................................................... 151 13.4.1.1 setting 13.4.1.2 operation 13.4.1.3 auto capture 13.4.1.4 register buffer configuration 13.4.2 external trigger timer mode ........................................................................................................................................... 155 13.4.2.1 setting 13.4.2.2 operation 13.4.2.3 auto capture 13.4.2.4 register buffer configuration 13.4.3 event counter mode ....................................................................................................................................................... 157 13.4.3.1 setting 13.4.3.2 operation 13.4.3.3 auto capture 13.4.3.4 register buffer configuration 13.4.4 window mode ................................................................................................................................................................ 159 13.4.4.1 setting 13.4.4.2 operation 13.4.4.3 auto capture 13.4.4.4 register buffer configuration 13.4.5 pulse width measurement mode .................................................................................................................................... 161 13.4.5.1 setting 13.4.5.2 operation 13.4.5.3 capture process 13.4.6 programmable pulse generate (ppg) mode ................................................................................................................... 164 13.4.6.1 setting 13.4.6.2 operation 13.4.6.3 register buffer configuration 13.5 noise canceller ....................................................................................................................167 13.5.1 setting ............................................................................................................................................................................ 167 13.6 revision history .................................................................................................................. 168 14. 8-bit timer counter (tc0) 14.1 configuration ....................................................................................................................... 170 14.2 control ................................................................................................................................. 171 14.2.1 timer counter 00 ............................................................................................................................................................171 14.2.2 timer counter 01 ............................................................................................................................................................173 14.2.3 common to timer counters 00 and 01 ............................................................................................................................175 iv
14.2.4 operation modes and usable source clocks ................................................................................................................... 177 14.3 low power consumption function ..................................................................................... 178 14.4 functions ..............................................................................................................................179 14.4.1 8-bit timer mode .............................................................................................................................................................179 14.4.1.1 setting 14.4.1.2 operation 14.4.1.3 double buffer 14.4.2 8-bit event counter mode ............................................................................................................................................... 182 14.4.2.1 setting 14.4.2.2 operation 14.4.2.3 double buffer 14.4.3 8-bit pulse width modulation (pwm) output mode ....................................................................................................... 184 14.4.3.1 setting 14.4.3.2 operations 14.4.3.3 double buffer 14.4.4 8-bit programmable pulse generate (ppg) output mode ............................................................................................... 189 14.4.4.1 setting 14.4.4.2 operation 14.4.4.3 double buffer 14.4.5 16-bit timer mode ...........................................................................................................................................................193 14.4.5.1 setting 14.4.5.2 operations 14.4.5.3 double buffer 14.4.6 16-bit event counter mode ............................................................................................................................................. 197 14.4.6.1 setting 14.4.6.2 operations 14.4.6.3 double buffer 14.4.7 12-bit pulse width modulation (pwm) output mode ..................................................................................................... 199 14.4.7.1 setting 14.4.7.2 operations 14.4.7.3 double buffer 14.4.8 16-bit programmable pulse generate (ppg) output mode ............................................................................................. 205 14.4.8.1 setting 14.4.8.2 operations 14.4.8.3 double buffer 14.5 revision history .................................................................................................................. 209 15. real time clock (rtc) 15.1 configuration ....................................................................................................................... 211 15.2 control ................................................................................................................................. 211 15.3 function ............................................................................................................................... 212 15.3.1 low power consumption function ............................................................................................................................... 212 15.3.2 enabling/disabling the real time clock operation .......................................................................................................... 212 15.3.3 selecting the interrupt generation interval ..................................................................................................................... 212 15.4 real time clock operation ................................................................................................. 213 15.4.1 enabling the real time clock operation .......................................................................................................................... 213 15.4.2 disabling the real time clock operation ......................................................................................................................... 213 16. asynchronous serial interface (uart) 16.1 configuration ....................................................................................................................... 216 16.2 control ................................................................................................................................. 217 16.3 low power consumption function ..................................................................................... 221 16.4 protection to prevent uart0cr1 and uart0cr2 registers from being changed ....... 222 16.5 activation of stop, idle0 or sleep0 mode ................................................................... 223 16.5.1 transition of register status ............................................................................................................................................223 16.5.2 transition of txd pin status ......................................................................................................................................... 223 16.6 transfer data format ........................................................................................................... 224 16.7 infrared data format transfer mode .................................................................................. 224 v
16.8 transfer baud rate .............................................................................................................. 225 16.8.1 transfer baud rate calculation method ...........................................................................................................................226 16.8.1.1 bit width adjustment using uart0cr2 16.8.1.2 calculation of set values of uart0cr2 and uart0dr 16.9 data sampling method ........................................................................................................ 229 16.10 received data noise rejection ......................................................................................... 231 16.11 transmit/receive operation .............................................................................................. 232 16.11.1 data transmit operation ................................................................................................................................................232 16.11.2 data receive operation ................................................................................................................................................. 232 16.12 status flag ......................................................................................................................... 233 16.12.1 parity error ................................................................................................................................................................... 233 16.12.2 framing error .............................................................................................................................................................. 234 16.12.3 overrun error ............................................................................................................................................................... 235 16.12.4 receive data buffer full ............................................................................................................................................. 238 16.12.5 transmit busy flag ...................................................................................................................................................... 239 16.12.6 transmit buffer full .................................................................................................................................................... 239 16.13 receiving process .............................................................................................................. 240 16.14 ac properties .....................................................................................................................242 16.14.1 irda properties ............................................................................................................................................................ 242 16.15 revision history ................................................................................................................ 243 17. synchronous serial interface (sio) 17.1 configuration ....................................................................................................................... 246 17.2 control ................................................................................................................................. 247 17.3 low power consumption function ..................................................................................... 250 17.4 functions ..............................................................................................................................251 17.4.1 transfer format .............................................................................................................................................................. 251 17.4.2 serial clock .................................................................................................................................................................... 251 17.4.3 transfer edge selection .................................................................................................................................................. 251 17.5 transfer modes .................................................................................................................... 253 17.5.1 8-bit transmit mode ........................................................................................................................................................ 253 17.5.1.1 setting 17.5.1.2 starting the transmit operation 17.5.1.3 transmit buffer and shift operation 17.5.1.4 operation on completion of transmission 17.5.1.5 stopping the transmit operation 17.5.2 8-bit receive mode ........................................................................................................................................................258 17.5.2.1 setting 17.5.2.2 starting the receive operation 17.5.2.3 operation on completion of reception 17.5.2.4 stopping the receive operation 17.5.3 8-bit transmit/receive mode ........................................................................................................................................... 262 17.5.3.1 setting 17.5.3.2 starting the transmit/receive operation 17.5.3.3 transmit buffer and shift operation 17.5.3.4 operation on completion of transmission/reception 17.5.3.5 stopping the transmit/receive operation 17.6 ac characteristics ............................................................................................................... 267 17.7 revision history .................................................................................................................. 268 18. serial bus interface (sbi) 18.1 communication format ....................................................................................................... 270 18.1.1 i2c bus ........................................................................................................................................................................... 270 18.1.2 free data format ............................................................................................................................................................. 271 18.2 configuration ....................................................................................................................... 272 18.3 control ................................................................................................................................. 273 vi
18.4 functions ..............................................................................................................................276 18.4.1 low power consumption function ............................................................................................................................... 276 18.4.2 selecting the slave address match detection and the general call detection .......................................................276 18.4.3 selecting the number of clocks for data transfer and selecting the acknowledgement or non-acknowledgment mode ...... 276 18.4.3.1 number of clocks for data transfer 18.4.3.2 output of an acknowledge signal 18.4.4 serial clock .................................................................................................................................................................... 278 18.4.4.1 clock source 18.4.4.2 clock synchronization 18.4.5 master/slave selection .................................................................................................................................................... 280 18.4.6 transmitter/receiver selection ........................................................................................................................................280 18.4.7 start/stop condition generation ...................................................................................................................................... 280 18.4.8 interrupt service request and release .............................................................................................................................. 281 18.4.9 setting of serial bus interface mode ............................................................................................................................... 282 18.4.10 software reset .............................................................................................................................................................. 282 18.4.11 arbitration lost detection monitor ................................................................................................................................282 18.4.12 slave address match detection monitor ....................................................................................................................... 284 18.4.13 general call detection monitor .......................................................................................................................... 284 18.4.14 last received bit monitor ............................................................................................................................................. 285 18.4.15 slave address and address recognition mode specification ......................................................................................... 285 18.5 data transfer of i2c bus ..................................................................................................... 286 18.5.1 device initialization ....................................................................................................................................................... 286 18.5.2 start condition and slave address generation ................................................................................................................. 286 18.5.3 1-word data transfer ....................................................................................................................................................... 287 18.5.3.1 when sbi0sr2 is "1" (master mode) 18.5.3.2 when sbi0sr2 is "0" (slave mode) 18.5.4 stop condition generation .............................................................................................................................................. 290 18.5.5 restart ............................................................................................................................................................................ 291 18.6 ac specifications ................................................................................................................ 293 18.7 revision history .................................................................................................................. 295 19. key-on wakeup (kwu) 19.1 configuration ....................................................................................................................... 297 19.2 control ................................................................................................................................. 298 19.3 functions ..............................................................................................................................299 20. 10-bit ad converter (adc) 20.1 configuration ....................................................................................................................... 301 20.2 control ................................................................................................................................. 302 20.3 functions .............................................................................................................................306 20.3.1 single mode ................................................................................................................................................................... 306 20.3.2 repeat mode .................................................................................................................................................................. 306 20.3.3 ad operation disable and forced stop of ad operation ................................................................................................ 307 20.4 register setting ................................................................................................................... 308 20.5 starting stop/idle0/slow modes ................................................................................. 308 20.6 analog input voltage and ad conversion result .............................................................. 309 20.7 precautions about the ad converter ................................................................................... 310 20.7.1 analog input pin voltage range ...................................................................................................................................... 310 20.7.2 analog input pins used as input/output ports .................................................................................................................310 20.7.3 noise countermeasure .................................................................................................................................................... 310 20.8 revision history .................................................................................................................. 311 vii
21. input/output circuit 21.1 control pins ......................................................................................................................... 313 22. electrical characteristics 22.1 absolute maximum ratings ............................................................................................... 315 22.2 operating conditions ........................................................................................................... 316 22.3 dc characteristics .............................................................................................................. 317 22.4 ad conversion characteristics .......................................................................................... 318 22.5 power-on reset circuit characteristics ............................................................................... 319 22.6 voltage detecting circuit characteristics ........................................................................... 320 22.7 ac characteristics ............................................................................................................... 321 22.8 oscillating condition ........................................................................................................... 322 22.9 handling precaution ............................................................................................................ 323 22.10 revision history ................................................................................................................ 324 23. package dimensions viii
cmos 8-bit microcontroller tmp89ch42 the tmp89ch42 is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 16384 bytes of mask rom. product no. rom (mask rom) ram package flash mcu emulation chip TMP89CH42UG 16384 bytes 2048 bytes lqfp44-p-1010-0.80b tmp89fh42ug * tmp89c900xbg note : * ; under development 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c1 series - instruction execution time : 100 ns (at 10 mhz) 122 s (at 32.768 khz) - 133 types & 732 basic instructions 2. 25 interrupt sources (external : 6 internal : 19 , except reset) 3. input / output ports (40 pins) note : two of above pins can not be used for the i/o port, because they should be connected with the high frequency osc input. - large current output: 8 pins (typ. 20ma) 4. watchdog timer - interrupt or reset can be selected by the program. 5. power-on reset circuit 6. voltage detection circuit 7. divider output function 8. time base timer 9. 16-bit timer counter (tca) : 2 ch - timer, external trigger, event counter, window, pulse width measurement, ppg output modes 10. 8-bit timer counter (tc0) : 4 ch - timer, event counter, pwm, ppg output modes - usable as a 16-bit timer, 12-bit pwm output and 16-bit ppg output by the cascade connection of two channels. 11. real time clock 12. uart : 1ch 13. uart/sio : 1ch note : one sio channel can be used at the same time. 14. i 2 c/sio : 1ch 15. key-on wake-up : 8 ch 16. 10-bit successive approximation type ad converter - analog input : 8ch 17. clock operation mode control circuit : 2 circuit single clock mode / dual clock mode 18. low power consumption operation (8 mode) tmp89ch42 page 1 ra000
- stop mode: oscillation stops. (battery/capacitor back-up.) - slow1 mode: low power consumption operation using low-frequency clock.(high-frequency clock stop.) - slow2 mode: low power consumption operation using low-frequency clock.(high-frequency clock oscillate.) - idle0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using high frequency clock. released when the reference time set to tbt has elapsed. - idle1 mode: the cpu stops, and peripherals operate using high frequency clock. release by interruputs(cpu restarts). - idle2 mode: cpu stops and peripherals operate using high and low frequency clock. release by interruputs. (cpu restarts). - sleep0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using low frequency clock. released when the reference time set to tbt has elapsed. - sleep1 mode: cpu stops, and peripherals operate using low frequency clock. release by interruput.(cpu restarts). 19. wide operation voltage: 4.3 v to 5.5 v at 10mhz /32.768 khz 2.7 v to 5.5 v at 4.2 mhz /32.768 khz 2.2 v to 5.5 v at 2mhz /32.768 khz tmp89ch42 1.1 features page 2 ra000
1.2 pin assignment p90 (txd1/rxd1) p77 (int4) p76 (int3) p75 (int2) p74 ( dvo) p47 (ain7/kwi7) p46 (ain6/kwi6) p45 (ain5/kwi5) p44 (ain4/kwi4) p43 (ain3/kwi3) p42 (ain2/kwi2) (txd1/rxd1) p91 p41 (ain1/kwi1) ( pwm02/ ppg02/tc02) p80 p40 (ain0/kwi0) ( pwm03/ ppg03/tc03) p81 varef/avdd ( pwm00/ ppg00/tc00) p70 p27 ( pwm01/ ppg01/tc01) p71 p26 ( ppga0/tca0) p72 p25 (sclk0) ( ppga1/tca1) p73 p24 (scl0/si0) (so0/rxd0/txd0) pb4 p23 (sda0/so0) (si0/txd0/rxd0) pb5 p22 (sclk0) (sclk0) pb6 p21 (rxd0/txd0/si0) pb7 p20 (txd0/rxd0/so0) vss (xin) p00 (xout) p01 mode vdd (xtin) p02 (xtout) p03 ( reset) p10 ( stop/ int5) p11 ( int0) p12 (int1) p13 figure 1-1 pin assignment tmp89ch42 page 3 ra000
1.3 block diagram figure 1-2 block diagram tmp89ch42 1.3 block diagram page 4 ra000
1.4 pin names and functions table 1-1 pin names and functions (1/3) pin name input/output functions p03 xtout io o port03 low frequency osc output p02 xtin io i port02 low frequency osc input p01 xout io o port01 high frequency osc output p00 xin io i port00 high frequency osc input p13 int1 io i port13 external interrupt 1 input p12 int0 io i port12 external interrupt 0 input p11 int5 stop io i i port11 external interrupt 5 input stop mode release input p10 reset io i port10 reset signal input p27 io port27 p26 io port26 p25 sclk0 io io port25 serial clock input/output 0 p24 scl0 si0 io io i port24 i2c bus clock input/output 0 serial data input 0 p23 sda0 so0 io io o port23 i2c bus data input/output 0 serial data output 0 p22 sclk0 io io port22 serial clock input/output 0 p21 rxd0 txd0 si0 io i o i port21 uart data input 0 uart data output 0 serial data input 0 p20 txd0 rxd0 so0 io o i o port20 uart data output 0 uart data input 0 serial data output 0 tmp89ch42 page 5 ra000
table 1-2 pin names and functions (2/3) pin name input/output functions p47 ain7 kwi7 io i i port47 analog input 7 key-on wake-up input 7 p46 ain6 kwi6 io i i port46 analog input 6 key-on wake-up input 6 p45 ain5 kwi5 io i i port45 analog input 5 key-on wake-up input 5 p44 ain4 kwi4 io i i port44 analog input 4 key-on wake-up input 4 p43 ain3 kwi3 io i i port43 analog input 3 key-on wake-up input 3 p42 ain2 kwi2 io i i port42 analog input 2 key-on wake-up input 2 p41 ain1 kwi1 io i i port41 analog input 1 key-on wake-up input 1 p40 ain0 kwi0 io i i port40 analog input 0 key-on wake-up input 0 p77 int4 io i port77 external interrupt 4 input p76 int3 io i port76 external interrupt 3 input p75 int2 io i port75 external interrupt 2 input p74 dvo io o port74 divider output p73 tca1 ppga1 io i o port73 tca1 input ppga1 output p72 tca0 ppga0 io i o port72 tca0 input ppga0 output p71 tc01 ppg01 pwm01 io i o o port71 tc01 input ppg01 output pwm01 output tmp89ch42 1.4 pin names and functions page 6 ra000
table 1-2 pin names and functions (3/3) pin name input/output functions p70 tc00 ppg00 pwm00 io i o o port70 tc00 input ppg00 output pwm00 output p81 tc03 ppg03 pwm03 io i o o port81 tc03 input ppg03 output pwm03 output p80 tc02 ppg02 pwm02 io i o o port80 tc02 input ppg02 output pwm02 output p91 rxd1 txd1 io i o port91 uart data input 1 uart data output 1 p90 txd1 rxd1 io o i port90 uart data output 1 uart data input 1 pb7 io portb7 pb6 sclk0 io io portb6 serial clock input/output 0 pb5 rxd0 txd0 si0 io i o i portb5 uart data input 0 uart data output 0 serial data input 0 pb4 txd0 rxd0 so0 io o i o portb4 uart data output 0 uart data input 0 serial data output 0 mode i test pin for out-going test (fix to low level). varef / avdd i analog reference voltage input pin for a/d conversion. / an- alog power supply pin. vdd i vdd pin vss i gnd pin tmp89ch42 page 7 ra000
tmp89ch42 1.4 pin names and functions page 8 ra000
2. cpu core 2.1 configuration the cpu core consists of a cpu, a system clock controller and a reset circuit. this chapter describes the cpu core address space, the system clock controller and the reset circuit. 2.2 memory space the 870/c1 cpu memory space consists of a code area to be accessed as instruction operation codes and operands and a data area to be accessed as sources and destinations of transfer and calculation instructions. both the code and data areas have independent 64-kbyte address spaces. 2.2.1 code area the code area stores operation codes, operands, vector tables for vector call instructions and interrupt vector tables. the ram and the maskrom are mapped in the code area. 0x0000 swi instruction (0xff) is fetched. 0x003f 0x0040 ram (2048 bytes) 0x083f swi instruction (0xff) is fetched. swi instruction (0xff) is fetched. 0xbfff 0xc000 mask rom (16384 bytes) mask rom (16384 bytes) 0xffa0 vector table for vec- tor call instructions (32 bytes) vector table for vec- tor call instructions (32 bytes) 0xffbf 0xffcc interrupt vector table (52 bytes) interrupt vector table (52 bytes) 0xffff immediately after re- set release when the ram is mapped in the code area figure 2-1 memory map in the code area tmp89ch42 page 9 rb000
2.2.1.1 ram the ram is mapped in the data area immediately after reset release. by setting syscr3 to "1" and writing 0xd4 to syscr4, ram can be mapped to 0x0040to 0x083f in the code area to execute the program. at this time, by setting syscr to "1" and writing 0xd4 to syscr4, vector table for vector call instructions and interrupt except reset can be mapped to ram. note 1: when the ram is not mapped in the code area, the swi instruction is fetched from 0x0040 to 0x 083f. note2: the contents of the ram become unstable when the power is turned on and immediately after a reset is released. to execute the program by using the ram, transfer the program to be executed in the initialization routine. system control register 3 syscr3 (0x0fde) 7 6 5 4 3 2 1 0 bit symbol - - - - - rvctr rarea (rstdis) read/write r r r r r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 rarea specifies mapping of the ram in the code area 0 : the ram is not mapped from 0x0040 to 0x083f in the code area. 1 : the ram is mapped from 0x0040 to 0x083f in the code area. rvctr specifies mapping of the vector ta- ble for vector call instructions and interrupts vector table for vector call instruc- tions vector table for interrupt 0 : 0xffa0 to 0xffbf in the code area 0xffcc to 0xffff in the code area 1 : 0x01a0 to 0x01bf in the code area 0x01cc to 0x01fd in the code area note 1: the value of syscr3 is invalid until 0xd4 is written into syscr4. note 2: to assign vector address areas to ram, set syscr3 to "1" and syscr3 to "1". note 3: bits 7 to 3 of syscr3 are read as "0". system control register 4 syscr4 (0x0fdf) 7 6 5 4 3 2 1 0 bit symbol syscr4 read/write w after reset 0 0 0 0 0 0 0 0 syscr4 writes the syscr3 data control code. 0xb2 : 0xd4 : 0x71 : enables the contents of syscr3. enables the contents of syscr3 and syscr3 . enables the contents of irstsr others : invalid note 1: syscr4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit oper- ation. note 2: after syscr3 is modified, syscr4 should be written 0xb2 (enable code for syscr3) in normal mode when fcgck is fc/4 (cgcr=00). otherwise, syscr3 may be enabled at unexpected tim- ing. note 3: after irstsr is modified, syscr4 should be written 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. tmp89ch42 2. cpu core 2.2 memory space page 10 rb000
system control status register 4 syssr4 (0x0fdf) 7 6 5 4 3 2 1 0 bit symbol - - - - - rvctrs rareas (rstdis) read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 rareas status of mapping of the ram in the code area 0 : 1 : the enabled syscr3 data is "0". the enabled syscr3 data is "1". rvctrs status of mapping of the vector ad- dress in the area 0 : 1 : the enabled syscr3 data is "0". the enabled syscr3 data is "1". note:bits 7 to 3 of syssr4 are read as "0". example: program transfer (transfer the program saved in the data area to the ram.) ld hl, transfer_start_address ; destination ram address ld de, program_start_address ; source rom address ld bc, byte_of_program ; number of bytes of the program to be executed -1 trans_ram: ld a, (de) ; reading the program to be transferred ld (hl), a ; writing the program to be transferred inc hl ; destination address increment inc de ; source address increment dec bc ; have all the programs been transferred? j f, trans_ram 2.2.1.2 maskrom the maskrom is mapped to 0xc000 to 0xffff in the code area after reset release. tmp89ch42 page 11 rb000
2.2.2 data area the data area stores the data to be accessed as sources and destinations of transfer and calculation instructions. the sfr, the ram and maskrom are mapped in the data area. 0x0000 sfr1 (64 bytes) 0x003f 0x0040 ram (2048 bytes) 0x083f 0xff is read 0x0e40 sfr3 (192 bytes) 0x0eff 0x0f00 sfr2 (256 bytes) 0x0fff 0x1000 0xff is read 0xbfff 0xc000 mask rom (16384 bytes) 0xffff figure 2-2 memory map in the data area 2.2.2.1 sfr the sfr is mapped to 0x0000 to 0x003f (sfr1), 0x0f00 to 0x0fff (sfr2) and 0x0e40 to 0x0eff (sfr3) in the data area after reset release. note:don't access the reserved sfr. 2.2.2.2 ram the ram is mapped to 0x0040 to 0x083f in the data area after reset release. note: the contents of the ram become unstable when the power is turned on and immediately after a reset is released. to execute the program by using the ram, transfer the program to be executed in the initialization routine. tmp89ch42 2. cpu core 2.2 memory space page 12 rb000
example: ram initialization program ld hl, ram_top_address ; head of address of the ram to be initialized ld a, 0x00 ; initialization data ld bc, byte_of_clear_bytes ; number of bytes of ram to be initialized -1 clr_ram: ld (hl), a ; initialization of the ram inc hl ; initialization address increment dec bc ; have all the rams been initialized? j f, clr_ram 2.2.2.3 maskrom the maskrom is mapped to 0xc000 to 0xffff in the data area after reset release. tmp89ch42 page 13 rb000
2.3 system clock controller 2.3.1 configuration the system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up counter and an operation mode control circuit. figure 2-3 system clock controller 2.3.2 control the system clock controller is controlled by system control register 1 (syscr1), system control register 2 (syscr2), the warm-up counter control register (wuccr), the warm-up counter data register (wucdr) and the clock gear control register (cgcr). system control register 1 syscr1 (0x0fdc) 7 6 5 4 3 2 1 0 bit symbol stop relm outen dv9ck - - - - read/write r/w r/w r/w r/w r r r r after reset 0 0 0 0 1 0 0 0 stop activates the stop mode 0 : 1 : operate the cpu and the peripheral circuits stop the cpu and the peripheral circuits (activate the stop mode) relm selects the stop mode release method 0 : edge-sensitive release mode (release the stop mode at the rising edge of the stop mode release signal) 1 : level-sensitive release mode (release the stop mode at the "h" level of the stop mode release signal) outen selects the port output state in the stop mode 0 : 1 : high impedance output hold dv9ck selects the input clock to stage 9 of the divider 0 : 1 : fcgck/2 9 fs/4 note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: bits 2, 1 and 0 of syscr1 are read as "0". bit 3 is read as "1". tmp89ch42 2. cpu core 2.3 system clock controller page 14 rb000 high-frequency clock oscillation circuit clock gear ( 1/4, 1/2, 1) warm-up counter fcgck dv9ck fcgcksel intwuc interrupt request xen/xten stop system clock oscillation/stop control clock generator xin xout xtin xtout fc fs 1/4 timing generator operation mode control circuit syscr1 tbtcr cgcr syscr2 wuccr wucdr low-frequency clock oscillation circuit
note 3: if the stop mode is activated with syscr1 set at "0", the port internal input is fixed to "0". therefore, an external interrupt may be set at the falling edge, depending on the pin state when the stop mode is activated. note 4: the p11 pin is also used as the stop pin. when the stop mode is activated, the pin reverts to high impedance state and is put in input mode, regardless of the state of syscr1. note 5: writing of the second byte data will be executed improperly if the operation is switched to the stop state by an instruction, such as ldw, which executes 2-byte data transfer at a time. note 6: don't set sysck1 to "1" before the oscillation of the low-frequency clock oscillation circuit becomes stable. note 7: in the slow1/2 or sleep1 mode, fs/4 is input to stage 9 of the divider, regardless of the state of syscr1< dv9ck >. system control register 2 syscr2 (0x0fdd) 7 6 5 4 3 2 1 0 bit symbol - xen xten sysck idle tghalt - - read/write r r/w r/w r/w r/w r/w r r after reset 0 1 0 0 0 0 0 0 xen controls the high-frequency clock oscillation circuit 0 : 1 : stop oscillation continue or start oscillation xten controls the low-frequency clock os- cillation circuit 0 : 1 : stop oscillation continue or start oscillation sysck selects a system clock 0 : 1 : gear clock (fcgck) (normal1/2 or idle1/2 mode) low-frequency clock (fs/4) (slow1/2 or sleep1 mode) idle cpu and wdt control (idle1/2 or sleep1 mode) 0 : 1 : operate the cpu and the wdt stop the cpu and the wdt (activate idle1/2 or sleep1 mode) tghalt tg control (idle0 or sleep0 mode) 0 : 1 : enable the clock supply from the tg to all the peripheral circuits disable the clock supply from the tg to the peripheral circuits except the tbt (activate idle0 or sleep0 mode) note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: wdt: watchdog timer, tg: timing generator note 3: don't set both syscr2 and syscr2 to "1" simultaneously. note 4: writing of the second byte data will be executed improperly if the operation is switched to the idle state by an instruction, such as ldw, which executes 2-byte data transfer at a time. note 5: when the idle1/2 or sleep1 mode is released, syscr2 is cleared to "0" automatically. note 6: when the idle0 or sleep0 mode is released, syscr2 is cleared to "0" automatically. note 7: bits 7, 1 and 0 of syscr2 are read as "0". warm-up counter control register wuccr (0x0fcd) 7 6 5 4 3 2 1 0 bit symbol wucrst - - - wucdiv wucsel - read/write w r r r r/w r/w r after reset 0 0 0 0 1 1 0 1 wucrst resets and stops the warm-up coun- ter 0 : 1 : - clear and stop the counter wucdiv selects the frequency division of the warm-up counter source clock 00 : 01 : 10 : 11 : source clock source clock / 2 source clock / 2 2 source clock / 2 3 wucsel selects the warm-up counter source clock 0 : 1 : select the high-frequency clock (fc) select the low-frequency clock (fs) note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: wuccr is cleared to "0" automatically, and need not be cleared to "0" after being set to "1". note 3: bits 7 to 4 of wuccr are read as "0". bit 0 is read as "1". tmp89ch42 page 15 rb000
note 4: before starting the warm-up counter operation, set the source clock and the frequency division rate at wuccr and set the warm-up time at wucdr. warm-up counter data register wucdr (0x0fce) 7 6 5 4 3 2 1 0 bit symbol wucdr read/write r/w after reset 0 1 1 0 0 1 1 0 wucdr warm-up time setting note 1: don't start the warm-up counter operation with wucdr set at "0x00". clock gear control register cgcr (0x0fcf) 7 6 5 4 3 2 1 0 bit symbol - - - - - - fcgcksel read/write r r r r r r r/w after reset 0 0 0 0 0 0 0 0 fcgcksel clock gear setting 00 : 01 : 10 : 11 : fcgck = fc / 4 fcgck = fc / 2 fcgck = fc reserved note 1: fcgck: gear clock [hz], fc: high-frequency clock [hz] note 2: don't change cgcr in the slow mode. note 3: bits 7 to 2 of cgcr are read as "0". 2.3.3 functions 2.3.3.1 clock generator the clock generator generates the basic clock for the system clocks to be supplied to the cpu core and peripheral circuits. it contains two oscillation circuits: one for the high-frequency clock and the other for the low-frequency clock. the oscillation circuit pins are also used as ports p0. for the setting to use them as ports, refer to the chapter of i/o ports. to use ports p00 and p01 as the high-frequency clock oscillation circuits (the xin and xout pins), set p0fc0 to "1" and then set syscr2 to "1". to use ports p02 and p03 as the low-frequency clock oscillation circuits (the xtin and xtout pins), set p0fc2 to "1" and then set syscr2 to "1". the high-frequency (fc) clock and the low-frequency (fs) clock can easily be obtained by connecting an oscillator between the xin and xout pins and between the xtin and xtout pins respectively. clock input from an external oscillator is also possible. in this case, external clocks are applied to the xin/ xtin pins and the xout/xtout pins are kept open. tmp89ch42 2. cpu core 2.3 system clock controller page 16 rb000
enabling/disabling the oscillation of the high-frequency clock oscillation circuit and the low-frequency clock oscillation circuit and switching the pin function to ports are controlled by the software and hardware. the software control is executed by syscr2, syscr2 and the p0 port function control register p0fc. the hardware control is executed by reset release and the operation mode control circuit when the operation is switched to the stop mode as described in "2.3.5 operation mode control circuit". note: no hardware function is available for external direct monitoring of the basic clock. the oscillation fre- quency can be adjusted by programming the system to output pulses at a certain frequency to a port (for example, a clock output) with interrupts disabled and the watchdog timer disabled and monitoring the output. an adjustment program must be created in advance for a system that requires adjustment of the oscillation frequency. to prevent the dead lock of the cpu core due to the software-controlled enabling/disabling of the oscil- lation, an internal factor reset is generated depending on the combination of values of the clock selected as the main system clock, syscr2, syscr2 and the p0 port function control register p0fc0. table 2-1 prohibited combinations of oscillation enable register conditions p0fc0 syscr2 syscr2 syscr2 state don't care 0 0 dont care all the oscillation circuits are stopped. dont care dont care 0 1 the low-frequency clock (fs) is selected as the main system clock, but the low-frequency clock oscillation circuit is stop- ped. dont care 0 dont care 0 the high-frequency clock (fc) is selected as the main system clock, but the high-frequency clock oscillation circuit is stop- ped. 0 1 dont care dont care the high-frequency clock oscillation circuit is allowed to os- cillate, but the port is set as a general-purpose port. note: it takes a certain period of time after syscr2 is changed before the main system clock is switched. if the currently operating oscillation circuit is stopped before the main system clock is switch- ed, the internal condition becomes as shown in table 2-1 and a system clock reset occurs. for details of clock switching, refer to "2.3.6 operation mode control". figure 2-4 examples of oscillator connection 2.3.3.2 clock gear the clock gear is a circuit that selects a gear clock (fcgck) obtained by dividing the high-frequency clock (fc) and inputs it to the timing generator. selects a divided clock at cgcr. two machine cycles are needed after cgcr is changed before the gear clock (fcgck) is changed. tmp89ch42 page 17 rb000 xin high-frequency clock xout (a) crystal or ceramic oscillator xin xout (b) external oscillator (open) xtin low-frequency clock xtout (c) crystal oscillator xtin xtout (d) external oscillator (open)
the gear clock (fcgck) may be longer than the set clock width, immediately after cgcr is changed. immediately after reset release, the gear clock (fcgck) becomes the clock that is a quarter of the high- frequency clock (fc). table 2-2 gear clock (fcgck) cgcr fcgck 00 fc / 4 01 fc / 2 10 fc 11 reserved note: don't change cgcr in the slow mode. this may stop the gear clock (fcgck) from being changed. 2.3.3.3 timing generator the timing generator is a circuit that generates system clocks to be supplied to the cpu core and the peripheral circuits, from the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). the timing generator has the following functions: 1. generation of the main system clock (fm) 2. generation of clocks for the timer counter, the time base timer and other peripheral circuits figure 2-5 configuration of timing generator (1) configuration of timing generator the timing generator consists of a main system clock generator, a prescaler, a 21-stage divider and a machine cycle counter. 1. main system clock generator this circuit selects the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs) for the main system clock (fm) to operate the cpu core. clearing syscr2 to "0" selects the gear clock (fcgck). setting it to "1" selects the clock that is a quarter of the low-frequency clock (fs). tmp89ch42 2. cpu core 2.3 system clock controller page 18 rb000 main system clock generator machine cycle counter syscr2 syscr1 gear clock fcgck prescaler divider multiplexer a timer counter, time base timer and other peripheral circuits divider b s y main system clock fm a quarter of the basic clock for the low-frequency clock
it takes a certain period of time after syscr2 is changed before the main system clock is switched. if the currently operating oscillation circuit is stopped before the main system clock is switched, the internal condition becomes as shown in table 2-1 and a system clock reset occurs. for details of clock switching, refer to "2.3.6 operation mode control". 2. prescaler and divider these circuits divide fcgck. the divided clocks are supplied to the timer counter, the time base timer and other peripheral circuits. when both syscr1 and syscr2 are "0", the input clock to stage 9 of the divider becomes the output of stage 8 of the divider. when syscr1 or syscr2 is "1", the input clock to stage 9 of the divider becomes fs/4. when syscr2 is "1", the outputs of stages 1 to 8 of the divider and prescaler are stopped. the prescaler and divider are cleared to "0" at a reset and at the end of the warm-up operation that follows the release of stop mode. 3. machine cycle instruction execution is synchronized with the main system clock (fm). the minimum instruction execution unit is called a "machine cycle". one machine cycle corresponds to one main system clock. there are a total of 11 different types of instructions for the tlcs-870/c1 series: 10 types ranging from 1-cycle instructions, which require one machine cycle for execution, to 10-cycle instructions, which require 10 machine cycles for execution, and 13-cycle instructions, which require 13 machine cycles for execution. 2.3.4 warm-up counter the warm-up counter is a circuit that counts the high-frequency clock (fc) and the low-frequency clock (fs), and it consists of a source clock selection circuit, a 3-stage frequency division circuit and a 14-stage counter. the warm-up counter is used to secure the time after a power-on reset is released before the supply voltage becomes stable and secure the time after the stop mode is released or the operation mode is changed before the oscillation by the oscillation circuit becomes stable. figure 2-6 warm-up counter circuit tmp89ch42 page 19 rb000 s z d c b a s z a b clock for high-frequency clock oscillation circuit (fc) clock for low-frequency clock oscillation circuit (fs) com- parator wucdr syscr2 syscr1 wuccr enable/disable counting up xen xten stop intwuc interrupt enable cpu operation wucsel wucdiv wucrst warm-up counter controller 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 1 2 3 4 5 6 7 1 2 3
2.3.4.1 warm-up counter operation when the oscillation is enabled by the hardware (1) when a power-on reset is released or a reset is released the warm-up counter serves to secure the time after a power-on reset is released before the supply voltage becomes stable and the time after a reset is released before the oscillation by the high-frequency clock oscillation circuit becomes stable. when the power is turned on and the supply voltage exceeds the power-on reset release voltage, the warm-up counter reset signal is released. at this time, the cpu and the peripheral circuits are held in the reset state. a reset signal initializes wuccr to "0" and wuccr to "11", which se- lects the high-frequency clock (fc) as the input clock to the warm-up counter. when a reset is released for the warm-up counter, the high-frequency clock (fc) is input to the warm- up counter, and the 14-stage counter starts counting the high-frequency clock (fc). when the upper 8 bits of the warm-up counter become equal to wucdr, counting is stopped and a reset is released for the cpu and the peripheral circuits. wucdr is initialized to 0x66 after reset release, which makes the warm-up time 0x66 2 9 /fc[s]. note: the clock output from the oscillation circuit is used as the input clock to the warm-up counter. the warm-up time contains errors because the oscillation frequency is unstable until the oscil- lation circuit becomes stable. (2) when the stop mode is released the warm-up counter serves to secure the time after the oscillation is enabled by the hardware before the oscillation becomes stable at the release of the stop mode. the high-frequency clock (fc) or the low-frequency clock (fs), which generates the main system clock when the stop mode is activated, is selected as the input clock for frequency division circuit, regardless of wuccr. before the stop mode is activated, select the division rate of the input clock to the warm-up counter at wuccr and set the warm-up time at wucdr. when the stop mode is released, the 14-stage counter starts counting the input clock selected in the frequency division circuit. when the upper 8 bits of the warm-up counter become equal to wucdr, counting is stopped and the operation is restarted by an instruction that follows the stop mode activation instruction. clock that generates the main system clock when the stop mode is activated wuccr wuccr counter input clock warm-up time fc dont care 00 fc 2 6 / fc to 255 x 2 6 / fc 01 fc / 2 2 7 / fc to 255 x 2 7 / fc 10 fc / 2 2 2 8 / fc to 255 x 2 8 / fc 11 fc / 2 3 2 9 / fc to 255 x 2 9 / fc fs don't care 00 fs 2 6 / fs to 255 x 2 6 / fs 01 fs / 2 2 7 / fs to 255 x 2 7 / fs 10 fs / 2 2 2 8 / fs to 255 x 2 8 / fs 11 fs / 2 3 2 9 / fs to 255 x 2 9 / fs note 1: when the operation is switched to the stop mode during the warm-up for the oscillation enabled by the software, the warm-up counter holds the value at the time, and restarts counting after the stop mode is released. in this case, the warm-up time at the release of the stop mode becomes insufficient. don't switch the operation to the stop mode during the warm-up for the oscillation enabled by the software. tmp89ch42 2. cpu core 2.3 system clock controller page 20 rb000
note 2: the clock output from the oscillation circuit is used as the input clock to the warm-up counter. the warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. set the sufficient time for the oscillation start property of the oscillator. 2.3.4.2 warm-up counter operation when the oscillation is enabled by the software the warm-up counter serves to secure the time after the oscillation is enabled by the software before the oscillation becomes stable, at a mode change from normal1 to normal2 or from slow1 to slow2. select the input clock to the frequency division circuit at wuccr. select the input clock to the 14-stage counter at wuccr. after the warm-up time is set at wucdr, setting syscr2 or syscr2 to "1" allows the stopped oscillation circuit to start oscillation and the 14-stage counter to start counting the selected input clock. when the upper 8 bits of the counter become equal to wucdr, an intwuc interrupt occurs, counting is stopped and the counter is cleared. set wuccr to "1" to discontinue the warm-up operation. by setting it to "1", the count-up operation is stopped, the warm-up counter is cleared, and wuccr is cleared to "0". syscr2 and syscr2 hold the values when wuccr is set to "1". to restart the warm-up operation, syscr2 or syscr2 must be cleared to "0". note:the warm-up counter starts counting when syscr2 or syscr2 is changed from "0" to "1". the counter will not start counting by writing "1" to syscr2 or syscr2 when it is in the state of "1". wuccr wuccr counter input clock warm-up time 0 00 fc 2 6 / fc to 255 x 2 6 / fc 01 fc / 2 2 7 / fc to 255 x 2 7 / fc 10 fc / 2 2 2 8 / fc to 255 x 2 8 / fc 11 fc / 2 3 2 9 / fc to 255 x 2 9 / fc 1 00 fs 2 6 / fs to 255 x 2 6 / fs 01 fs / 2 2 7 / fs to 255 x 2 7 / fs 10 fs / 2 2 2 8 / fs to 255 x 2 8 / fs 11 fs / 2 3 2 9 / fs to 255 x 2 9 / fs note: the clock output from the oscillation circuit is used as the input clock to the warm-up counter. the warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. set the sufficient time for the oscillation start property of the oscillator. 2.3.5 operation mode control circuit the operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock (fm). there are three operating modes: the single-clock mode, the dual-clock mode and the stop mode. these modes are controlled by the system control registers (syscr1 and syscr2). figure 2-7 shows the operating mode transition diagram. tmp89ch42 page 21 rb000
2.3.5.1 single-clock mode only the gear clock (fcgck) is used for the operation in the single-clock mode. the main system clock (fm) is generated from the gear clock (fcgck). therefore, the machine cycle time is 1/fcgck [s]. the gear clock (fcgck) is generated from the high-frequency clock (fc). in the single-clock mode, the low-frequency clock generation circuit pins p02 (xtin) and p03 (xtout) can be used as the i/o ports. (1) normal1 mode in this mode, the cpu core and the peripheral circuits operate using the gear clock (fcgck). the normal1 mode becomes active after reset release. (2) idle1 mode in this mode, the cpu and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck). the idle1 mode is activated by setting syscr2 to "1" in the normal1 mode. when the idle1 mode is activated, the cpu and the watchdog timer stop. when the interrupt latch enabled by the interrupt enable register efr becomes "1", the idle1 mode is released to the normal1 mode. when the imf (interrupt master enable flag) is "1" (interrupts enabled), the operation returns normal after the interrupt processing is completed. when the imf is "0" (interrupts disabled), the operation is restarted by the instruction that follows the idle1 mode activation instruction. (3) idle0 mode in this mode, the cpu and the peripheral circuits stop, except the oscillation circuits and the time base timer. in the idle0 mode, the peripheral circuits stop in the states when the idle0 mode is activated or become the same as the states when a reset is released. for operations of the peripheral circuits in the idle0 mode, refer to the section of each peripheral circuit. the idle0 mode is activated by setting syscr2 to "1" in the normal1 mode. when the idle0 mode is activated, the cpu stops and the timing generator stops the clock supply to the peripheral circuits except the time base timer. when the falling edge of the source clock selected at tbtcr is detected, the idle0 mode is released, the timing generator starts the clock supply to all the peripheral circuits and the normal1 mode is restored. note that the idle0 mode is activated and restarted, regardless of the setting of tbtcr. when the idle0 mode is activated with tbtcr set at "1", the inttbt interrupt latch is set after the normal mode is restored. when the imf is "1" and the ef5 (the individual interrupt enable flag for the time base timer) is "1", the operation returns normal after the interrupt processing is completed. tmp89ch42 2. cpu core 2.3 system clock controller page 22 rb000
when the imf is "0" or when the imf is "1" and the ef5 (the individual interrupt enable flag for the time base timer) is "0", the operation is restarted by the instruction that follows the idle0 mode acti- vation instruction. 2.3.5.2 dual-clock mode the gear clock (fcgck) and the low-frequency clock (fs) are used for the operation in the dual-clock mode. the main system clock (fm) is generated from the gear clock (fcgck) in the normal2 or idle2 mode, and generated from the clock that is a quarter of the low-frequency clock (fs) in the slow1/2 or sleep0/1 mode. therefore, the machine cycle time is 1/fcgck [s] in the normal2 or idle2 mode and is 4/fs [s] in the slow1/2 or sleep0/1 mode. p02 (xtin) and p03 (xtout) are used as the low-frequency clock oscillation circuit pins. (these pins cannot be used as i/o ports in the dual-clock mode.) the operation of the tlcs-870/c1 series becomes the single-clock mode after reset release. to operate it in the dual-clock mode, allow the low-frequency clock to oscillate at the beginning of the program. (1) normal2 mode in this mode, the cpu core operates using the gear clock (fcgck), and the peripheral circuits operate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). (2) slow2 mode in this mode, the cpu core and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). in the slow mode, some peripheral circuits become the same as the states when a reset is released. for operations of the peripheral circuits in the slow mode, refer to the section of each peripheral circuit. set syscr2 to switch the operation mode from normal2 to slow2 or from slow2 to normal2. in the slow2 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (3) slow1 mode in this mode, the high-frequency clock oscillation circuit stops operation and the cpu core and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). this mode requires less power to operate the high-frequency clock oscillation circuit than in the slow2 mode. in the slow mode, some peripheral circuits become the same as the states when a reset is released. for operations of the peripheral circuits in the slow mode, refer to the section of each peripheral circuit. set syscr2 to switch the operation between the slow1 and slow2 modes. in the slow1 or sleep1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (4) idle2 mode in this mode, the cpu and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). tmp89ch42 page 23 rb000
the idle2 mode can be activated and released in the same way as for the idle1 mode. the operation returns to the normal2 mode after this mode is released. (5) sleep1 mode in this mode, the high-frequency clock oscillation circuit stops operation, the cpu and the watchdog timer stop, and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). in the sleep1 mode, some peripheral circuits become the same as the states when a reset is released. for operations of the peripheral circuits in the sleep1 mode, refer to the section of each peripheral circuit. the sleep1 mode can be activated and released in the same way as for the idle1 mode. the operation returns to the slow1 mode after this mode is released. in the slow1 or sleep1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (6) sleep0 mode in this mode, the high-frequency clock oscillation circuit stops operation, the time base timer operates using the clock that is a quarter of the low-frequency clock (fs), and the core and the peripheral circuits stop. in the sleep0 mode, the peripheral circuits stop in the states when the sleep0 mode is activated or become the same as the states when a reset is released. for operations of the peripheral circuits in the sleep0 mode, refer to the section of each peripheral circuit. the sleep0 mode can be activated and released in the same way as for the idle0 mode. the operation returns to the slow1 mode after this mode is released. in the sleep0 mode, the cpu stops and the timing generator stops the clock supply to the peripheral circuits except the time base timer. 2.3.5.3 stop mode in this mode, all the operations in the system, including the oscillation circuits, are stopped and the internal states in effect before the system was stopped are held with low power consumption. in the stop mode, the peripheral circuits stop in the states when the stop mode is activated or become the same as the states when a reset is released. for operations of the peripheral circuits in the stop mode, refer to the section of each peripheral circuit. the stop mode is activated by setting syscr1 to "1". the stop mode is released by the stop mode release signals. after the warm-up time has elapsed, the operation returns to the mode that was active before the stop mode, and the operation is restarted by the instruction that follows the stop mode activation instruction. tmp89ch42 2. cpu core 2.3 system clock controller page 24 rb000
2.3.5.4 transition of operation modes note 1: the normal1 and normal2 modes are generically called the normal mode; the slow1 and slow2 modes are called the slow mode; the idle0, idle1 and idle2 modes are called the idle mode; and the sleep0 and sleep1 are called the sleep mode. note 2: the mode is released by the falling edge of the source clock selected at tbtcr. figure 2-7 operation mode transition diagram tmp89ch42 page 25 rb000 idle0 mode reset warm-up that follows reset release normal1 mode stop normal2 mode slow2 mode slow1 mode idle0 mode idle2 mode sleep1 mode sleep0 mode (a) single-clock mode (b) dual-clock mode syscr2 = "1" syscr1 = "1" syscr2 = "1" syscr1 = "1" syscr2 = "1" syscr1 = "1" interrupt interrupt stop mode release signal stop mode release signal stop mode release signal interrupt syscr2 = ?1? syscr2 = "0" syscr2 = "1" syscr2 = "0" syscr2 = "1" syscr2 = "0" syscr2 = "1" reset release warm-up completed syscr2 = "1" (note 2) (note 2)
table 2-3 operation modes and conditions operation mode oscillation circuit cpu core watchdog timer time base timer ad converter other periph- eral circuits machine cy- cle time high-fre- quency low-fre- quency single clock reset oscillation stop reset reset reset reset reset 1 / fcgck [s] normal1 operate operate operate operate operate idle1 stop stop idle0 stop stop stop stop stop ? dual clock normal2 oscillation oscillation operate with the high fre- quency operate with the high / low frequency operate operate operate 1 / fcgck [s] idle2 stop stop slow2 operate with the low fre- quency operate with the low fre- quency stop 4/ fs [s] slow1 stop operate with the low fre- quency operate with the low fre- quency sleep1 stop stop sleep0 stop stop stop stop ? 2.3.6 operation mode control 2.3.6.1 stop mode the stop mode is controlled by system control register 1 (syscr1) and the stop mode release signals. (1) start the stop mode the stop mode is started by setting syscr1 to "1". in the stop mode, the following states are maintained: 1. both the high-frequency and low-frequency clock oscillation circuits stop oscillation and all internal operations are stopped. 2. the data memory, the registers and the program status word are all held in the states in effect before stop mode was started. the port output latch is determined by the value of syscr1. 3. the prescaler and the divider of the timing generator are cleared to "0". 4. the program counter holds the address of the instruction 2 ahead of the instruction (e.g., [set (syscr1).7]) which started the stop mode. (2) release the stop mode the stop mode is released by the following stop mode release signals. it is also released by a reset by the reset pin, a power-on reset and a reset by the voltage detection circuits. when a reset is released, the warm-up starts. after the warm-up is completed, the normal1 mode becomes active. 1. release by the stop pin 2. release by key-on wakeup 3. release by the voltage detection circuits tmp89ch42 2. cpu core 2.3 system clock controller page 26 rb000
note: during the stop period (from the start of the stop mode to the end of the warm-up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after the stop mode is released. before starting the stop mode, therefore, disable interrupts. also, before enabling interrupts after stop mode is released, clear unnecessary interrupt latches. 1. release by the stop pin release the stop mode by using the stop pin. the stop mode release by the stop pin includes the level-sensitive release mode and the edge-sensitive release mode, either of which can be selected at syscr1. the stop pin is also used as the p11 port and the int5 (external interrupt input 5) pin. - level-sensitive release mode the stop mode is released by setting the stop pin high. setting syscr1 to "1" selects the level-sensitive release mode. this mode is used for the capacitor backup when the main power supply is cut off and the long term battery backup. even if an instruction for starting the stop mode is executed while the stop pin input is high, the stop mode does not start. thus, to start the stop mode in the level-sensitive release mode, it is necessary for the program to first confirm that the stop pin input is low. this can be confirmed by testing the port by the software or using interrupts note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was started, regard- less of wuccr. example: starting the stop mode from normal mode after testing p00 port. (warm-up time at release of the stop mode is about 300s at fc= 10mhz.) ld (syscr1), 0x40 ; sets up the level-sensitive release mode sstoph: test (p0prd). 5 ; wait until stop pin becomes l level. j f, sstoph ld (wuccr), 0x01 ; wuccr = 00 (no division) (note) ld (wucdr),0x2f ; sets the warm-up time ; 300s / 6.4s = 46.9 round up to 0x2f di ; imf = 0 set (syscr1).7 ; starts the stop mode note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was started, regardless of wuccr. example: starting the stop mode from the slow mode with an int5 interrupt (warm-up time at release of the stop mode is about 450ms at fs=32.768 khz.) pint5: test (p0prd).5 ; to reject noise, the stop mode does not start j f, sint5 ; if the stop pin input is high. ld (syscr1), 0x40 ; sets up the level-sensitive release mode ld (wuccr), 0x03 ; wuccr = 00 (no division) (note) ld (wucdr),0xe8 ; sets the warm-up time ; 450 ms/1.953 ms = 230.4 round up to 0xe8 di ; imf = 0 set (syscr1).7 ; starts the stop mode sint5: reti tmp89ch42 page 27 rb000
note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was started, regardless of wuccr. note: even if the stop pin input returns to low after the warm-up starts, the stop mode is not restarted. figure 2-8 level-sensitive release mode (example when the high-frequency clock oscillation circuit is selected) - edge-sensitive release mode in this mode, the stop mode is released at the rising edge of the stop pin input. setting syscr1 to "0" selects the edge-sensitive release mode. this is used in applications where a relatively short program is executed repeatedly at periodic intervals. this periodic signal (for example, a clock from a low-power con- sumption oscillator) is input to the stop pin. in the edge-sensitive release mode, the stop mode is started even when the stop pin input is high example: starting the stop mode from the normal mode (warm-up time at release of the stop mode is about 200s at fc=10 mhz.) ld (wuccr),0x01 ; wuccr = 00 (no division) (note) ld (wucdr),0x20 ; sets the warm-up time ; 200s / 6.4s = 31.25 round up to 0x20 di ; imf = 0 ld (syscr1) , 0x80 ; starts the stop mode with the edge-sensitive release mode selected note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was started, regardless of wuccr. note: if the rising edge is input to the stop pin within 1 machine cycle after syscr1 is set to "1", the stop mode will not be released. figure 2-9 edge-sensitive release mode (example when the high-frequency clock oscillation circuit is selected) 2. release by the key-on wakeup tmp89ch42 2. cpu core 2.3 system clock controller page 28 rb000 stop pin xout pin normal mode v ih warm-up stop mode stop mode the stop mode is started by the program. the stop mode is released by the hardware at the rising edge of the stop pin input. normal mode stop pin xout pin normal mode the stop mode is released by the hardware. normal mode v ih warm-up stop mode confirm by program that the stop pin input is low and start the stop mode. always released if the stop pin input is high.
the stop mode is released by inputting the prescribed level to the key-on wakeup pin. the level to release the stop mode can be selected from "h" and "l". for release by the key-on wakeup, refer to section "key-on wakeup". note: if the key-on wakeup pin input becomes the opposite level to the release level after the warm-up starts, the stop mode is not restarted. 3. release by the voltage detection circuits the stop mode is released by the supply voltage detection by the voltage detection circuits. if the voltage detection operation mode of the voltage detection circuits is set to "generates a voltage detection reset signal", the stop mode is released and a reset is applied as soon as the supply voltage becomes lower than the detection voltage. when the supply voltage becomes equal to or higher than the detection voltage of the voltage detection circuits, the reset is released and the warm-up starts. after the warm-up is completed, the normal1 mode becomes active. for details, refer to the section of the voltage detection circuits. note: if the supply voltage becomes equal to or higher than the detection voltage within 1 ma- chine cycle after syscr1 is set to "1", the stop mode will not be released. (3) stop mode release operation the stop mode is released in the following sequence: 1. oscillation starts. for the oscillation start operation in each mode, refer to "table 2-4 oscil- lation start operation at release of the stop mode". 2. warm-up is executed to secure the time required to stabilize oscillation. the internal operations remain stopped during warm-up. the warm-up time is set by the warm-up counter, depending on the oscillator characteristics. 3. after the warm-up time has elapsed, the normal operation is restarted by the instruction that follows the stop mode start instruction. at this time, the prescaler and the divider of the timing generator are cleared to "0". note: when the stop mode is released with a low hold voltage, the following cautions must be ob- served. the supply voltage must be at the operating voltage level before releasing the stop mode. the reset pin input must also be "h" level, rising together with the supply voltage. in this case, if an external time constant circuit has been connected, the reset pin input voltage will increase at a slower pace than the power supply voltage. at this time, there is a danger that a reset may occur if the input voltage level of the reset pin drops below the non-inverting high-level input voltage (hysteresis input). table 2-4 oscillation start operation at release of the stop mode operation mode before the stop mode is started high-frequency clock low-frequency clock oscillation start operation after release single-clock mode normal1 high-frequency clock oscillation cir- cuit - the high-frequency clock oscillation circuit starts os- cillation. the low-frequency clock oscillation circuit stops os- cillation. dual-clock mode normal2 high-frequency clock oscillation cir- cuit low-frequency clock oscillation cir- cuit the high-frequency clock oscillation circuit starts os- cillation. the low-frequency clock oscillation circuit starts os- cillation. slow1 - low-frequency clock oscillation cir- cuit the high-frequency clock oscillation circuit stops os- cillation. the low-frequency clock oscillation circuit starts os- cillation. tmp89ch42 page 29 rb000
note: when the operation returns to the normal2 mode, fc is input to the frequency division circuit of the warm-up counter. 2.3.6.2 idle1/2 and sleep1 modes the idle1/2 and sleep1 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following states are maintained during these modes. 1. the cpu and the watchdog timer stop their operations. the peripheral circuits continue to operate. 2. the data memory, the registers, the program status word and the port output latches are all held in the status in effect before idle1/2 or sleep1 mode was started. 3. the program counter holds the address of the instruction 2 ahead of the instruction which starts the idle1/2 or sleep1 mode. figure 2-10 idle1/2 and sleep 1 modes tmp89ch42 2. cpu core 2.3 system clock controller page 30 rb000 cpu and wdt stop interrupt processing reset yes no no no no imf = "1" reset input yes yes (interrupt release mode) (normal release mode) interrupt request starting idle1/2 mode or sleep1 mode by an instruction execution of the instruction which follows the idle1/2 mode or sleep1 mode start instruction
(1) start the idle1/2 and sleep1 modes after the interrupt master enable flag (imf) is set to "0", set the individual interrupt enable flag (ef) to "1", which releases idle1/2 and sleep1 modes. to start the idle1/2 or sleep1 mode, set syscr2 to "1". if the release condition is satisfied when it is attempted to start the idle1/2 or sleep1 mode, syscr2 remains cleared and the idle1/2 or sleep1 mode will not be started. note 1: when a watchdog timer interrupt is generated immediately before the idle1/2 or sleep1 mode is started, the watchdog timer interrupt will be processed but the idle1/2 or sleep1 mode will not be started. note 2: before starting the idle1/2 or sleep1 mode, enable the interrupt request signals to be generated to release the idle1/2 or sleep1 mode and set the individual interrupt enable flag. (2) release the idle1/2 and sleep1 modes the idle1/2 and sleep1 modes include a normal release mode and an interrupt release mode. these modes are selected at the interrupt master enable flag (imf). after releasing idle1/2 or sleep1 mode, syscr2 is automatically cleared to "0" and the operation mode is returned to the mode pre- ceding the idle1/2 or sleep1 mode. the idle1/2 and sleep1 modes are also released by a reset by the reset pin , a power-on reset and a reset by the voltage detection circuits. after releasing the reset, the warm-up starts. after the warm-up is completed, the normal1 mode becomes active. ? normal release mode (imf = "0") the idle1/2 or sleep1 mode is released when the interrupt latch enabled by the individual interrupt enable flag (ef) is "1". the operation is restarted by the instruction that follows the idle1/2 or sleep1 mode start instruction. normally, the interrupt latch (il) of the interrupt source used for releasing must be cleared to "0" by load instructions. ? interrupt release mode (imf = "1") the idle1/2 or sleep1 mode is released when the interrupt latch enabled by the individual interrupt enable flag (ef) is "1". after the interrupt is processed, the operation is restarted by the instruction that follows the idle1/2 or sleep1 mode start instruction. 2.3.6.3 idle0 and sleep0 modes the idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following states are maintained during the idle0 and sleep0 modes: ? the timing generator stops the clock supply to the peripheral circuits except the time base timer. ? the data memory, the registers, the program status word and the port output latches are all held in the states in effect before the idle0 or sleep0 mode was started. ? the program counter holds the address of the instruction 2 ahead of the instruction which starts the idle0 or sleep0 mode. tmp89ch42 page 31 rb000
figure 2-11 idle0 and sleep0 modes ? start the idle0 and sleep0 modes stop (disable) the peripherals such as a timer counter. to start the idle0 or sleep0 mode, set syscr2 to "1". ? release the idle0 and sleep0 modes the idle0 and sleep0 modes include a normal release mode and an interrupt release mode. these modes are selected at the interrupt master enable flag (imf), the individual interrupt enable flag (ef5) for the time base timer and tbtcr. after releasing the idle0 or sleep0 mode, syscr2 is automatically cleared to "0" and the operation mode is returned to the mode preceding the idle0 or sleep0 mode. if tbtcr has been set at "1", the inttbt interrupt latch is set. the idle0 and sleep0 modes are also released by a reset by the reset pin , a power-on reset and a reset by the voltage detection circuits. when a reset is released, the warm-up starts. after the warm-up is completed, the normal1 mode becomes active. tmp89ch42 2. cpu core 2.3 system clock controller page 32 rb000 reset yes no no "0" yes yes (interrupt release mode) (normal release mode) yes "1" no no stopping peripherals by instructions cpu and wdt stop interrupt processing reset input tbt source clock falling edge tbtcr tbt interrupt enabled imf = "1" starting idle0 or sleep0 mode by an instruction execution of the instruction which follows the idle0 or sleep0 mode start instruction
(1) normal release mode (imf, ef5, tbtcr = "0") the idle0 or sleep0 mode is released when the falling edge of the source clock selected at tbtcr is detected. after the idle0 or sleep0 mode is released, the operation is restarted by the instruction that follows the idle0 or sleep0 mode start instruction. when tbtcr is "1", the time base timer interrupt latch is set. (2) interrupt release mode (imf, ef5, tbtcr = "1") the idle0 or sleep0 mode is released when the falling edge of the source clock selected at tbtcr is detected. after the release, the inttbt interrupt processing is started. note 1: the idle0 or sleep0 mode is released to the normal1 or slow1 mode by the asynchronous internal clock selected at tbtcr. therefore, the period from the start to the release of the mode may be shorter than the time specified at tbtcr. note 2: when a watchdog timer interrupt is generated immediately before the idle0 or sleep0 mode is started, the watchdog timer interrupt will be processed but the idle0 or sleep0 mode will not be started. 2.3.6.4 slow mode the slow mode is controlled by system control register 2 (syscr2). (1) switching from the normal2 mode to the slow1 mode set syscr2 to "1". when a maximum of 2/fcgck + 10/fs [s] has elapsed since syscr2 is set to "1", the main system clock (fm) is switched to fs/4. after switching, wait for 2 machine cycles or longer, and then clear syscr2 to "0" to turn off the high-frequency clock oscillator. if the oscillation of the low-frequency clock (fs) is unstable, confirm the stable oscillation at the warm- up counter before implementing the procedure described above. note 1: be sure to follow this procedure to switch the operation from the normal2 mode to the slow1 mode. note 2: it is also possible to allow the basic clock for the high-frequency clock to oscillate continuously to return to normal2 mode. however, be sure to turn off the oscillation of the basic clock for the high-frequency clock when the stop mode is started from the slow mode. note 3: after switching syscr2, be sure to wait for 2 machine cycles or longer before clearing syscr2 to "0". clearing it within 2 machine cycles causes a system clock reset. note 4: when the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the clock that is a quarter of the basic clock (fs) for the low-frequency clock. for the synchronization, fm is stopped for a period of 10/fs or shorter. tmp89ch42 page 33 rb000
figure 2-12 switching of the main system clock (fm) (switching from fcgck to fs/4) example 1: switching from the normal2 mode to the slow1 mode (when fc is used as the basic clock for the high- frequency clock) set (syscr2).4 ; syscr2 = 1 ; (switches the main system clock to the basic clock for the ; low-frequency clock for the slow2 mode) nop ; waits for 2 machine cycles nop clr (syscr2).6 ; syscr2 = 0 ; (turns off the high-frequency clock oscillation circuit) example 2: switching to the slow1 mode after the stable oscillation of the low-frequency clock oscillation circuit is confirmed at the warm-up counter (fs=32.768khz, warm-up time = about 100 ms) ; #### initialize routine #### set (p0fc).2 ; p0fc2 = 1 (uses p02/03 as oscillators) | | ld (wuccr), 0x02 ; wuccr = 00 (no division) ; wuccr = 1 (selects fs as the source clock) ld (wucdr), 0x33 ; sets the warm-up time ; (determines the time depending on the oscillator characteristics) ; 100 ms/1.95 ms = 51.2 round up to 0x33 set (eirl).4 ; enables intwuc interrupts set (syscr2).5 ; syscr2 = 1 ; (starts the low-frequency clock oscillation and starts the warm-up ; counter) | ; #### interrupt service routine of warm-up counter interrupts #### pintwuc: set (syscr2).4 ; syscr2 = 1 ; (switches the main system clock to the low-frequency clock) nop ; waits for 2 machine cycles nop clr (syscr2).6 ; syscr2 = 0 ; (turns off the high-frequency clock oscillation circuit) reti | tmp89ch42 2. cpu core 2.3 system clock controller page 34 rb000 gear clock (fcgck) when the rising edge of fcgck is detected twice after syscr2 is changed from 0 to 1, f is stopped for synchronization. when the rising edge of fs/4 is detected twice after fm is stopped, fm is switched to fs. quarter of the low-frequency clock (fs/4) main system clock syscr2 10/fs (max.)
vintwuc: dw pintwuc ; intwuc vector table (2) switching from the slow1 mode to the normal1 mode set syscr2 to "1" to enable the high-frequency clock (fc) to oscillate. confirm at the warm- up counter that the oscillation of the basic clock for the high-frequency clock has stabilized, and then clear syscr2 to "0". when a maximum of 8/fs + 2.5/fcgck [s] has elapsed since syscr2 is cleared to "0", the main system clock (fm) is switched to fcgck. after switching, wait for 2 machine cycles or longer, and then clear syscr2 to "0" to turn off the low-frequency clock oscillator. the slow mode is also released by a reset by the reset pin , a power-on reset and a reset by the voltage detection circuits. when a reset is released, the warm-up starts. after the warm-up is completed, the normal1 mode becomes active. note 1: be sure to follow this procedure to switch the operation from the slow1 mode to the normal1 mode. note 2: after switching syscr2, be sure to wait for 2 machine cycles or longer before clearing syscr2 to "0". clearing it within 2 machine cycles causes a system clock reset. note 3: when the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the clock that is a quarter of the basic clock (fs) for the low-frequency clock. for the synchronization, fm is stopped for a period of 2.5/fcgck [s] or shorter. note 4: when p0fc0 is "0", setting syscr2 to "1" causes a system clock reset. note 5: when syscr2 is set at "1", writing "1" to syscr2 does not cause the warm-up counter to start counting the source clock. figure 2-13 switching the main system clock (fm) (switching from fs/4 to fcgck) example : switching from the slow1 mode to the normal1 mode after the stability of the high-frequency clock oscillation circuit is confirmed at the warm-up counter (fc = 10 mhz, warm-up time = 4.0 ms) ; #### initialize routine #### set (p0fc).2 ; p0fc2 = 1 (uses p02/03 as oscillators) | | ld (wuccr), 0x09 ; wuccr = 10 (divided by 2) ; wuccr = 0 (selects fc as the source clock) ld (wucdr), 0x9d ; sets the warm-up time ; (determine the time depending on the frequency and the oscillator ; characteristics) ; 4ms / 25.6us = 156.25 round up to 0x9d tmp89ch42 page 35 rb000 gear clock (fcgck) when the rising edge of fs/4 is detected twice after syscr2 is changed from 1 to 0, f is stopped for synchronization. when the rising edge of fcgck is detected twice after fm is stopped, fm is switched to fcgck. quarter of the low-frequency clock (fs/4) main system clock syscr2 2.5/fcgck(max.)
set (eirl). 4 ; enables intwuc interrupts set (syscr2) .6 ; syscr2 = 1 ; (starts the oscillation of the high-frequency clock oscillation circuit) | ; #### interrupt service routine of warm-up counter interrupts #### pintwuc: clr (syscr2). 4 ; syscr2 = 0 ; (switches the main system clock to the gear clock) nop ; waits for 2 machine cycles nop clr (syscr2). 5 ; syscr2 = 0 ; (turns off the low-frequency clock oscillation circuit) reti | vintwuc: dw pintwuc ; intwuc vector table tmp89ch42 2. cpu core 2.3 system clock controller page 36 rb000
2.4 reset control circuit the reset circuit controls the external and internal factor resets and initializes the system. 2.4.1 configuration the reset control circuit consists of the following reset signal generation circuits: 1. external reset input (external factor) 2. power-on reset (internal factor) 3. voltage detection reset 1 (internal factor) 4. voltage detection reset 2 (internal factor) 5. watchdog timer reset (internal factor) 6. system clock reset (internal factor) 7. trimming data reset (internal factor) figure 2-14 reset control circuit 2.4.2 control the reset control circuit is controlled by system control register 3 (syscr3), system control register 4 (syscr4), system control status register (syssr4) and the internal factor reset detection status register (irstsr). system control register 3 syscr3 (0x0fde) 7 6 5 4 3 2 1 0 bit symbol - - - - - (rvctr) (rarea) rstdis read/write r r r r r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 rstdis external reset input enable register 0 : 1 : enables the external reset input. disables the external reset input. note 1: the enabled syscr3 is initialized by a power-on reset only, and cannot be initialized by an external reset input or internal factor reset. the value written in syscr3 is reset by a power-on reset, external reset input or internal factor reset. note 2: the value of syscr3 is invalid until 0xb2 is written into syscr4. note 3: after syscr3 is modified, syscr4 should be written 0xb2 (enable code for syscr3) in nor- mal1 mode when fcgck is fc/4 (cgcr=00). otherwise, syscr3 may be enabled at unexpec- ted timing. tmp89ch42 page 37 rb000 p10(reset) internal factor reset detection status register, voltage detection circuit reset signal external reset input enable reset signal warm-up counter reset signal system clock control circuit warm-up counter cpu/peripheral circuits reset signal trimming data reset signal system clock reset signal watchdog timer reset signal voltage detection reset 2 signal power-on reset signal p10 port voltage detection reset 1 signal
note 4: bits 7 to 3 of syscr3 are read as "0". system control register 4 syscr4 (0x0fdf) 7 6 5 4 3 2 1 0 bit symbol syscr4 read/write w after reset 0 0 0 0 0 0 0 0 syscr4 writes the syscr3 data control code. 0xb2 : 0xd4 : 0x71 : others : enables the contents of syscr3 enables the contents of syscr3 and syscr3 enables the contents of irstsr invalid note 1: syscr4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit oper- ation. note 2: after syscr3 is modified, syscr4 should be written 0xb2 (enable code for syscr3) in normal mode when fcgck is fc/4 (cgcr=00). otherwise, syscr3 may be enabled at unexpected tim- ing. note 3: after irstsr is modified, syscr4 should be written 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. system control status register 4 syssr4 (0x0fdf) 7 6 5 4 3 2 1 0 bit symbol - - - - - (rvctrs) (rareas) rstdiss read/write r r r r r r r r after reset 0 0 0 0 0 0 0 0 rstdiss external reset input enable status 0 : 1 : the enabled syscr3 data is "0". the enabled syscr3 data is "1". note 1: the enabled syscr3 is initialized by a power-on reset only, and cannot be initialized by any other reset signals. the value written in syscr3 is reset by a power-on reset and other reset signals. note 2: bits 7 to 3 of syscr4 are read as "0". tmp89ch42 2. cpu core 2.4 reset control circuit page 38 rb000
internal factor reset detection status register irstsr (0x0fcc) 7 6 5 4 3 2 1 0 bit symbol fclr - trmds trmrf lvd2rf lvd1rf sysrf wdtrf read/write w r r r r r r r after reset 0 0 0 0 0 0 0 0 fclr flag initialization control 0 : 1 : - clears the internal factor reset flag to "0". trmds trimming data status 0 : 1 : - detect state of abnormal trimming data trmrf trimming data reset detection flag 0 : 1 : - detects the trimming data reset. lvd2rf voltage detection reset 2 detection flag 0 : 1 : - detects the voltage detection 2 reset. lvd1rf voltage detection reset 1 detection flag 0 : 1 : - detects the voltage detection 1 reset. sysrf system clock reset detection flag 0 : 1 : - detects the system clock reset. wdtrf watchdog timer reset detection flag 0 : 1 : - detects the watchdog timer reset. note 1: internal reset factor flag (irstsr) is initialized only by a power- on reset, an external reset input or irstsr . it is not initialized by an internal factor reset. note 2: care must be taken in system designing since the irstsr may not fulfill its functions due to disturbing noise and other effects. note 3: if syscr4 is set to 0x71 after irstsr is set to "1", internal factor reset flag is cleared to "0" and irstsr is automatically cleared to "0". note 4: after irstsr is modified, syscr4 should be written 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. note 5: bit 7, 6 of irstsr is read as "0". 2.4.3 functions the power-on reset, external reset input and internal factor reset signals are input to the warm-up circuit of the clock generator. during reset, the warm-up counter circuit is reset, and the cpu and the peripheral circuits are reset. after reset is released, the warm-up counter starts counting the high frequency clock (fc), and executes the warm-up operation that follows reset release. during the warm-up operation that follows reset release, the trimming data is loaded from the non-volatile exclusive use memory for adjustment of the ladder resistor that generates the comparison voltage for the power- on reset and the voltage detection circuits. when the warm-up operation that follows reset release is finished, the cpu starts execution of the program from the reset vector address stored in addresses 0xfffe to 0xffff. when a reset signal is input during the warm-up operation that follows reset release, the warm-up counter circuit is reset. the reset operation is common to the power-on reset, external reset input and internal factor resets, except for the initialization of some special function registers and the initialization of the voltage detection circuits. when a reset is applied, the peripheral circuits become the states as shown in table 2-5. tmp89ch42 page 39 rb000
table 2-5 initialization of built-in hardware by reset operation and its status after release built-in hardware during reset during the warm-up opera- tion that follows reset re- lease immediately after the warm-up operation that fol- lows reset release program counter (pc) 0xfffe 0xfffe 0xfffe stack pointer (sp) 0x00ff 0x00ff 0x00ff ram indeterminate indeterminate indeterminate general-purpose registers (w, a, b, c, d, e, h, l, ix and iy) indeterminate indeterminate indeterminate register bank selector (rbs) 0 0 0 jump status flag (jf) indeterminate indeterminate indeterminate zero flag (zf) indeterminate indeterminate indeterminate carry flag (cf) indeterminate indeterminate indeterminate half carry flag (hf) indeterminate indeterminate indeterminate sign flag (sf) indeterminate indeterminate indeterminate overflow flag (vf) indeterminate indeterminate indeterminate interrupt master enable flag (imf) 0 0 0 individual interrupt enable flag (ef) 0 0 0 interrupt latch (il) 0 0 0 high-frequency clock oscillation circuit oscillation enabled oscillation enabled oscillation enabled low-frequency clock oscillation circuit oscillation disabled oscillation disabled oscillation disabled warm-up counter reset start stop timing generator prescaler and divider 0 0 0 watchdog timer disabled disabled enabled voltage detection circuit disabled or enabled disabled or enabled disabled or enabled i/o port pin status hiz hiz hiz special function register refer to the sfr map. refer to the sfr map. refer to the sfr map. note:the voltage detection circuits are disabled by an external reset input or power-on reset only. tmp89ch42 2. cpu core 2.4 reset control circuit page 40 rb000
2.4.4 reset signal generating factors reset signals are generated by each factor as follows: 2.4.4.1 power-on reset the power-on reset is an internal reset that occurs when power is turned on. during power-up, a power-on reset signal is generated while the supply voltage is below the power-on reset release voltage. when the supply voltage rises above the power-on reset release voltage, the power-on reset signal is released. during power-down, a power-on reset signal is generated when the supply voltage falls below the power- on reset detection voltage. refer to "power-on reset circuit". 2.4.4.2 external reset input ( reset pin input) this is an external reset that is generated by the reset pin input. port p10 is also used as the reset pin, and it is configured as the reset pin at power-up. ? during power-up - when the supply voltage rises rapidly when the power supply rise time (t vdd ) is shorter than 5 [ms] with enough margin, the reset can be released by a power-on reset or an external reset ( reset pin input). the power-on reset logic and external reset ( reset pin input) logic are ored. this means that the tmp89ch42 is reset when either or both of these reset sources are asserted. therefore, the reset time is determined by the reset source with a longer reset period. if the reset pin level changes from low to high before the supply voltage rises above the power-on-reset release voltage (v proff ) (or if the reset pin level is high from the be- ginning), the reset time depends on the power-on reset. if the reset pin level changes from low to high after the supply voltage rises above v proff , the reset time depends on the external reset. in the former case, a warm-up period begins when the power-on reset signal is released. in the latter case, a warm-up period begins when the reset pin level becomes high. upon completion of the warm-up period, the cpu and peripheral circuits start operating (figure 2-15). - when the supply voltage rises slowly when the power supply rise time (t vdd ) is longer than 5 [ms], the reset must be released by using the reset pin. in this case, hold the reset pin low until the supply voltage rises to the operating voltage range and oscillation is stabilized. when this state is achieved, wait at least 5 [s] and then pull the reset pin high. changing the reset pin level to high starts a warm-up period. upon completion of the warm-up period, the cpu and peripheral circuits start operating (figure 2-15). tmp89ch42 page 41 rb000
figure 2-15 external reset input (during power-up) tmp89ch42 2. cpu core 2.4 reset control circuit page 42 rb000 operating voltage range v proff t vdd reset pin warm-up period (t pwup ) when the supply voltage rises rapidly (when the reset time depends on external reset) cpu and peripheral circuits start operating cpu and peripheral circuits reset power-on reset operating voltage range v proff 5 s or more t vdd reset pin warm-up period (t pwup ) when the supply voltage rises slowly cpu and peripheral circuits start operating cpu and peripheral circuits reset power-on reset operating voltage range v proff t vdd reset pin warm-up period (t pwup ) when the supply voltage rises rapidly (when the reset time depends on power-on reset) cpu and peripheral circuits start operating cpu and peripheral circuits reset power-on reset
? when the supply voltage is within the operating voltage range when the supply voltage is within the operating voltage range and stable oscillation is achieved, holding the reset pin low for 5 [ s] or longer generates a reset. then, changing the reset pin level to high starts a warm-up period. upon completion of the warm-up period, the cpu and peripheral circuits start operating (figure 2-16). figure 2-16 external reset input (when the power supply is stable) 2.4.4.3 voltage detection reset the voltage detection reset is an internal factor reset that occurs when it is detected that the supply voltage has reached a predetermined detection voltage. refer to "voltage detection circuit". 2.4.4.4 watchdog timer reset the watchdog timer reset is an internal factor reset that occurs when an overflow of the watchdog timer is detected. refer to "watchdog timer". 2.4.4.5 system clock reset the system clock reset is an internal factor reset that occurs when it is detected that the oscillation enable register is set to a combination that puts the cpu into deadlock. refer to "clock control circuit". 2.4.4.6 trimming data reset the trimming data reset is an internal factor reset that occurs when the trimming data latched in the internal circuit is broken down during operation due to noise or other factors. the trimming data is a data bit provided for adjustment of the ladder resistor that generates the comparison voltage for the power-on reset and the voltage detection circuits. this bit is loaded from the non-volatile exclusive use memory during the warm-up time that follows reset release (tpwup) and latched into the internal circuit. if the trimming data loaded from the non-volatile exclusive use memory during the warm-up operation that follows reset release is abnormal, irstsr is set to "1". tmp89ch42 page 43 rb000 operating voltage range reset pin warm-up period (t pwup ) cpu and peripheral circuits start operating cpu and peripheral circuits reset 5 s or more
when irstsr is read as "1" in the initialize routine immediately after reset release, the trim- ming data need to be reloaded by generating an internal factor reset, such as a system clock reset, and activating the warm-up operation again. if irstsr is still set to "1" after repeated reading, the detection voltage of the voltage detection circuit and power-on reset circuit does not satisfy the characteristic specified in the electric characteristics. design the system so that the system will not be damaged in such a case. 2.4.4.7 internal factor reset detection status register by reading the internal factor reset detection status register irstsr after the release of an internal factor reset, except the power-on reset, the factor which causes a reset can be detected. the internal factor reset detection status register is initialized by an external reset input or power-on re- set. set irstsr to "1" and write 0x71 to syscr4. this enables irstsr and the internal factor reset detection status register is clear to "0". irstsr is cleared to "0" automatically after initializing the internal factor reset detection status register. note 1: care must be taken in system designing since the irstsr may not fulfill its functions due to disturbing noise and other effects. note 2: after irstsr is modified, syscr4 should be written 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. 2.4.4.8 how to use the external reset input pin as a port to use the external reset input pin as a port, keep the external reset input pin at the "h" level until the power is turned on and the warm-up operation that follows reset release is finished. after the warm-up operation that follows reset release is finished, set p1pu0 to "1" and p1cr0 to "0", and connect a pull-up resistor for a port. then set syscr3 to "1" and write 0xb2 to syscr4. this disables the external reset function and makes the external reset input pin usable as a normal port. to use the pin as an external reset pin when it is used as a port, set p1pu0 to "1" and p1cr0 to "0" and connect the pull-up resistor to put the pin to the input mode. then clear syscr3 to "0" and write 0xb2 to syscr4. this enables the external reset function and makes the pin usable as the external reset input pin. note 1: if you switch the external reset input pin to a port or switch the pin used as a port to the external reset input pin, do it when the pin is stabilized at the "h" level. switching the pin function when the "l" level is input may cause a reset. note 2: if the external reset input is used as a port, the statement which clears syscr3 to "0" is not written in a program. by the abnormal execution of program, the external reset input set as a port may be changed as the external reset input at unexpected timing. note 3: after syscr3 is modified, syscr4 should be written 0xb2 (enable code for syscr3) in normal1 mode when fcgck is fc/4 (cgcr=00). otherwise, syscr3 may be enabled at unexpected timing. tmp89ch42 2. cpu core 2.4 reset control circuit page 44 rb000
2.5 revision history rev description ra002 "table 2-3 operation modes and conditions" added ad converter condition. "(2) release the stop mode" added new example program and note to level-sensitive release mode. ra003 "table 2-3 operation modes and conditions" revised character code error. "table 2-3 operation modes and conditions" added ad converter condition. "(2) release the stop mode" added new example program. ra004 "2.3.6 operation mode control" revised register name from vdcr2 to vdcr2. " internal factor reset detection status register" revised note. "2.4.4.2 external reset input (reset pin input)" revised description. rb000 revised p03 (xtin) and p04 (xtout) to p02 (xtin) and p03 (xtout). deleted srss function. tmp89ch42 page 45 rb000
tmp89ch42 2. cpu core 2.5 revision history page 46 rb000
3. interrupt control circuit the tmp89ch42 has a total of 25 interrupt sources excluding reset. interrupts can be nested with priorities. three of the internal interrupt sources are non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il), which hold interrupt requests, and have independent vector addresses. when a request for an interrupt is generated, its interrupt latch is set to "1", which requests the cpu to accept the interrupt. acceptance of interrupts is enabled or disabled by software using the interrupt master enable flag (imf) and individual enable flag (ef) for each interrupt source. if multiple maskable interrupts are generated simul- taneously, the interrupts are accepted in order of descending priority. the priorities are determined by the interrupt priority change control register (ilprs1-ilprs6) as levels and determined by the hardware as the basic priorities. however, there are no prioritized interrupt sources among non-maskable interrupts. interrupt sources enable condition interrupt latch vector address (mcu mode) basic priori- ty rvctr=0 enabled rvctr=1 enabled internal/ex- ternal (reset) non-maskable - 0xfffe - 1 internal intswi non-maskable - 0xfffc 0x01fc 2 internal intundef non-maskable - 0xfffc 0x01fc 2 internal intwdt non-maskable ill 0xfff8 0x01f8 2 internal intwuc imf and eirl = 1 ill 0xfff6 0x01f6 5 internal inttbt imf and eirl = 1 ill 0xfff4 0x01f4 6 internal intrxd0 / intsio0 imf and eirl = 1 ill 0xfff2 0x01f2 7 internal inttxd0 imf and eirl = 1 ill 0xfff0 0x01f0 8 external int5 imf and eirh = 1 ilh 0xffee 0x01ee 9 internal intvltd imf and eirh = 1 ilh 0xffec 0x01ec 10 internal intadc imf and eirh = 1 ilh 0xffea 0x01ea 11 internal intrtc imf and eirh = 1 ilh 0xffe8 0x01e8 12 internal inttc00 imf and eirh = 1 ilh 0xffe6 0x01e6 13 internal inttc01 imf and eirh = 1 ilh 0xffe4 0x01e4 14 internal inttca0 imf and eirh = 1 ilh 0xffe2 0x01e2 15 internal intsbi0/intsio0 imf and eirh = 1 ilh 0xffe0 0x01e0 16 external int0 imf and eire = 1 ile 0xffde 0x01de 17 external int1 imf and eire = 1 ile 0xffdc 0x01dc 18 external int2 imf and eire = 1 ile 0xffda 0x01da 19 external int3 imf and eire = 1 ile 0xffd8 0x01d8 20 external int4 imf and eire = 1 ile 0xffd6 0x01d6 21 internal inttca1 imf and eire = 1 ile 0xffd4 0x01d4 22 internal intrxd1 imf and eire = 1 ile 0xffd2 0x01d2 23 internal inttxd1 imf and eire = 1 ile 0xffd0 0x01d0 24 internal inttc02 imf and eird = 1 ild 0xffce 0x01ce 25 internal inttc03 imf and eird = 1 ild 0xffcc 0x01cc 26 - - - - - - - - - - - - - - note 1: to use the watchdog timer interrupt (intwdt), clear wdctr to "0" (it is set for the "reset request" after reset is released). for details, see "watchdog timer". note 2: vector address areas can be changed by the syscr3 setting. to assign vector address areas to ram, set syscr3 to "1" and syscr3 to "1". tmp89ch42 page 47 ra003
3.1 configuration figure 3-1 interrupt control circuit tmp89ch42 3. interrupt control circuit 3.1 configuration page 48 ra003 s a3 2 1 0 4 b q il 4 il 4 il 5 il 6 il 7 il 8 il 9 il 10 il 11 il 12 il 13 il 14 il 15 il 16 il 17 il 18 il 19 il 20 il 21 r s q imf r internal factor reset en intswi intundef intwdt interrupt source 4 interrupt source 5 interrupt source 6 interrupt source 7 interrupt source 8 interrupt source 9 interrupt source 10 interrupt source 11 interrupt source 12 interrupt source 13 interrupt source 14 interrupt source 15 interrupt source 16 interrupt source 17 interrupt source 18 interrupt source 19 interrupt source 20 decoder vector address generation priority encoder di instruction interrupt accept idle1/2,sleep1/2 mode clear request interrupt request imf (interrupt master enable flag) internal factor reset instruction to write ?0? to imf non-maskable interrupts maskable interrupts maskable interrupt priority change circuit ilprs1 ilprs2 ilprs3 ilprs4 s q il 3 r 5 4 3 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 data bus address bus il 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 [retn] instruction [ret1]1 instruction (only when the imf is set to ?1? before interrupt acceptance) (only when the imf is set to ?1? before interrupt acceptance) [ei] instruction instruction to write ?1? to imf il3 vector read signal il4 clear signal il4 vector read signal reading ilprs6 25 ef 25 to ef 4 il 25 interrupt source25 il 25 to il 4
3.2 interrupt latches (il25 to il3) an interrupt latch is provided for each interrupt source, except for a software interrupt and an undefined instruction execution interrupt. when an interrupt request is generated, the latch is set to "1", and the cpu is requested to accept the interrupt if its acceptance is enabled. the interrupt latch is cleared to "0" immediately after the interrupt is accepted. all interrupt latches are initialized to "0" during reset. the interrupt latches are located at addresses 0x0fe0, 0x0fe1, 0x0fe2, 0x0fe3 in sfr area. each latch can be cleared to "0" individually by an instruction. however, il2 and il3 interrupt latches cannot be cleared by instructions. do not use any read-modify-write instruction, such as a bit manipulation or operation instruction, because it may clear interrupt requests generated while the instruction is executed. interrupt latches cannot be set to "1" by using an instruction. writing "1" to an interrupt latch is equivalent to denying clearing of the interrupt latch, and not setting the interrupt latch. since interrupt latches can be read by instructions, the status of interrupt requests can be monitored by software. note: in the main program, before manipulating an interrupt latch (il), be sure to clear the master enable flag (imf) to "0" (disable interrupt by di instruction). then set the imf to "1" as required after operating the il (enable interrupt by ei instruction). in the interrupt service routine, the imf becomes "0" automatically and need not be cleared to "0" normally. however, if using multiple interrupt in the interrupt service routine, manipulate the il before setting the imf to "1". example 1: clears interrupt latches di ; imf 0 ld (ill), 0y00111111 ; il7 to il6 0 ld (ilh), 0y11101000 ; il12, il10 to il8 0 ei ; imf 1 example 2: reads interrupt latches ld wa, (ill) ; w ilh, a ill example 3: tests interrupt latches test (ill). 7 ; if il7=1 then jump jr f, sset ; tmp89ch42 page 49 ra003
3.3 interrupt enable register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (software interrupt, undefined instruction interrupt and watchdog interrupt). non-maskable interrupts are accepted regardless of the contents of the eir. the eir consists of the interrupt master enable flag (imf) and the individual interrupt enable flags (ef). these registers are located at addresses 0x003a, 0x003b, 0x003c, 0x003d in the sfr area, and they can be read and written by instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.3.1 interrupt master enable flag (imf) the interrupt master enable flag (imf) enables and disables the acceptance of all maskable interrupts. clearing the imf to "0" disables the acceptance of all maskable interrupts. setting the imf to "1" enables the acceptance of the interrupts that are specified by the individual interrupt enable flags. when an interrupt is accepted, the imf is stacked and then cleared to "0", which temporarily disables the subsequent maskable interrupts. after the interrupt service routine is executed, the stacked data, which was the status before interrupt acceptance, reloaded on the imf by return interrupt instruction [reti]/[retn]. the imf is located on bit 0 in eirl (address: 0x03a in sfr), and can be read and written by instructions. the imf is normally set and cleared by [ei] and [di] instructions respectively. during reset, the imf is initialized to "0". 3.3.2 individual interrupt enable flags (ef25 to ef4) each of these flags enables and disables the acceptance of its maskable interrupt. setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. during reset, all the individual interrupt enable flags are initialized to "0" and no maskable interrupts are accepted until the flags are set to "1". note: in the main program, before manipulating the interrupt enable flag (ef), be sure to clear the master enable flag (imf) to "0" (disable interrupt by di instruction). then set the imf to "1" as required after operating the ef (enable interrupt by ei instruction). in the interrupt service routine, the imf becomes "0" automatically and need not be cleared to "0" nor- mally. however, if using multiple interrupt in the interrupt service routine, manipulate the ef before setting the imf to "1". example: enables interrupts individually and sets imf di ; imf 0 ldw : (eirl), 0y1110100010100000 ; ; ef15 to ef13, ef11, ef7, ef5 1 note: imf should not be set. : ei ; imf 1 tmp89ch42 3. interrupt control circuit 3.3 interrupt enable register (eir) page 50 ra003
interrupt latch (ill) ill 7 6 5 4 3 2 1 0 (0x0fe0) bit symbol il7 il6 il5 il4 il3 - - - read/write r/w r/w r/w r/w r r r r after reset 0 0 0 0 0 0 0 0 function inttxd0 intrxd0 / intsio0 inttbt intwuc intwdt interrupt latch (ilh) ilh 7 6 5 4 3 2 1 0 (0x0fe1) bit symbol il15 il14 il13 il12 il11 il10 il9 il8 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function intsbi0/in- tsio0 inttca0 inttc01 inttc00 intrtc intadc intvltd int5 interrupt latch (ile) ile 7 6 5 4 3 2 1 0 (0x0fe2) bit symbol il23 il22 il21 il20 il19 il18 il17 il16 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function inttxd1 intrxd1 inttca1 int4 int3 int2 int1 int0 interrupt latch (ild) ild 7 6 5 4 3 2 1 0 (0x0fe3) bit symbol - - - - - - il25 il24 read/write r r r r r r r/w r/w after reset 0 0 0 0 0 0 0 0 function inttc03 inttc02 il25 to il4 interrupt latch read write 0: no interrupt request clears the interrupt request (notes 2 and 3) 1: interrupt request does not clear the interrupt re- quest (interrupt is not set by writing "1".) il3 0: 1: no interrupt request interrupt request - note 1: il3 is a read-only register. writing the register does not affect interrupt latch. note 2: in the main program, before manipulating an interrupt latch (il), be sure to clear the interrupt master enable flag (imf) to "0" (disable interrupt by di instruction). then set the imf to "1" as required after operating the il (enable interrupt by ei instruction). in the interrupt service routine, the imf becomes "0" automatically and need not be cleared to "0" normally. however, if using multiple interrupt in the interrupt service routine, manipulate the il before setting the imf to "1". note 3: do not clear il with read-modify-write instructions such as bit operations. note 4: when a read instruction is executed on ill, bits 0 to 2 are read as "0". other unused bits are read as "0". tmp89ch42 page 51 ra003
interrupt enable register (eirl) eirl 7 6 5 4 3 2 1 0 (0x003a) bit symbol ef7 ef6 ef5 ef4 - - - imf read/write r/w r/w r/w r/w r r r r/w after reset 0 0 0 0 0 0 0 0 function inttxd0 intrxd0 / intsio0 inttbt intwuc interrupt master ena- ble flag interrupt enable register (eirh) eirh 7 6 5 4 3 2 1 0 (0x003b) bit symbol ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function intsbi0/in- tsio0 inttca0 inttc01 inttc00 intrtc intadc intvltd int5 interrupt enable register (eire) eire 7 6 5 4 3 2 1 0 (0x003c) bit symbol ef23 ef22 ef21 ef20 ef19 ef18 ef17 ef16 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function inttxd1 intrxd1 inttca1 int4 int3 int2 int1 int0 interrupt enable register (eird) eird 7 6 5 4 3 2 1 0 (0x003d) bit symbol - - - - - - ef25 ef24 read/write r r r r r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function inttc03 inttc02 ef25 to ef4 individual interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts. enables the acceptance of all maskable interrupts. note 1: do not set the imf and the interrupt enable flag (ef15 to ef4) to "1" at the same time. note 2: in the main program, before manipulating the interrupt enable flag (ef), be sure to clear the master enable flag (imf) to "0" (disable interrupt by di instruction). then set the imf to "1" as required after operating the ef (enable interrupt by ei instruction) in the interrupt service routine, the imf becomes "0" automatically and need not be cleared to "0" normally. however, if using multiple interrupt in the interrupt service routine, manipulate the ef before setting the imf to "1". note 3: when a read instruction is executed on eirl, bits 3 to 1 are read as "0". other unused bits are read as "0". tmp89ch42 3. interrupt control circuit 3.3 interrupt enable register (eir) page 52 ra003
3.4 maskable interrupt priority change function the priority of maskable interrupts (il4 to il25) can be changed to four levels, levels 0 to 3, regardless of the basic priorities 5 to 26. interrupt priorities can be changed by the interrupt priority change control register (ilprs1 to ilprs6 ). to raise the interrupt priority, set the level to a larger number. to lower the interrupt priority, set the level to a smaller number. when different maskable interrupts are generated simultaneously at the same level, the interrupt with higher basic priority is processed preferentially. for example, when the ilprs1 register is set to 0xc0 and interrupts il4 and il7 are generated at the same time, il7 is preferentially processed (provided that ef4 and ef7 have been enabled). after reset is released, all maskable interrupts are set to priority level 0 (the lowest priority). note: in the main program, before manipulating the interrupt priority change control register (ilprs1 to 6), be sure to clear the master enable flag (imf) to "0" (disable interrupt by di instruction). set the imf to "1" as required after operating ilprs1 to 6 (enable interrupt by ei instruction). in the interrupt service routine, the imf becomes "0" automatically and need not be cleared to "0" normally. however, if using multiple interrupt in the interrupt service routine, manipulate ilprs1 to 6 before setting the imf to "1". interrupt priority change control register 1 ilprs1 7 6 5 4 3 2 1 0 (0x0ff0) bit symbol il07p il06p il05p il04p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il07p sets the interrupt priority of il7. 00: level 0 (lower priority) il06p sets the interrupt priority of il6. 01: level 1 il05p sets the interrupt priority of il5. 10: level 2 il04p sets the interrupt priority of il4. 11: level 3 (higher priority) interrupt priority change control register 2 ilprs2 7 6 5 4 3 2 1 0 (0x0ff1) bit symbol il11p il10p il09p il08p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il11p sets the interrupt priority of il11. 00: level 0 (lower priority) il10p sets the interrupt priority of il10. 01: level 1 il09p sets the interrupt priority of il9. 10: level 2 il08p sets the interrupt priority of il8. 11: level 3 (higher priority) interrupt priority change control register 3 ilprs3 7 6 5 4 3 2 1 0 (0x0ff2) bit symbol il15p il14p il13p il12p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il15p sets the interrupt priority of il15. 00: level 0 (lower priority) il14p sets the interrupt priority of il14. 01: level 1 il13p sets the interrupt priority of il13. 10: level 2 il12p sets the interrupt priority of il12. 11: level 3 (higher priority) tmp89ch42 page 53 ra003
interrupt priority change control register 4 ilprs4 7 6 5 4 3 2 1 0 (0x0ff3) bit symbol il19p il18p il17p il16p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il19p sets the interrupt priority of il19. 00: level 0 (lower priority) il18p sets the interrupt priority of il18. 01: level 1 il17p sets the interrupt priority of il17. 10: level 2 il16p sets the interrupt priority of il16. 11: level 3 (higher priority) interrupt priority change control register 5 ilprs5 7 6 5 4 3 2 1 0 (0x0ff4) bit symbol il23p il22p il21p il20p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 il23p sets the interrupt priority of il23. 00: level 0 (lower priority) il22p sets the interrupt priority of il22. 01: level 1 il21p sets the interrupt priority of il21. 10: level 2 il20p sets the interrupt priority of il20. 11: level 3 (higher priority) interrupt priority change control register 6 ilprs6 7 6 5 4 3 2 1 0 (0x0ff5) bit symbol - - il25p il24p read/write r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 - - 00: level 0 (lower priority) - - 01: level 1 il25p sets the interrupt priority of il25. 10: level 2 il24p sets the interrupt priority of il24. 11: level 3 (higher priority) tmp89ch42 3. interrupt control circuit 3.4 maskable interrupt priority change function page 54 ra003
3.5 interrupt sequence an interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to 0 by resetting or an instruction. interrupt acceptance sequence requires 8-machine cycles after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). 3.5.1 initial setting using an interrupt requires specifying an sp (stack pointer) for it in advance. the sp is a 16-bit register pointing at the start address of a stack. the sp is post-decremented when a subroutine call or a push instruction is executed or when an interrupt request is accepted. it is pre-incremented when a return or pop instruction is executed. therefore, the stack becomes deeper toward lower stack location addresses. be sure to reserve a stack area having an appropriate size based on the sp setting. the sp is initialized to 00ffh after a reset. if you need to change the sp, do so right after a reset or when the interrupt master enable flag (imf) is 0. example :sp setting ld sp, 023fh ; sp = 023fh ld sp, sp+04h ; sp = sp + 04h add sp, 0010h ; sp = sp + 0010h 3.5.2 interrupt acceptance processing interrupt acceptance processing is packaged as follows. 1. the interrupt master enable flag (imf) is cleared to 0 in order to disable the acceptance of any following interrupt. 2. the interrupt latch (il) for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the stack in sequence of psw + imf, pch, pcl. meanwhile, the stack pointer (sp) is decremented by 3. 4. the entry address (interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. 5. the instruction stored at the entry address of the interrupt service program is executed. note: when the contents of psw are saved on the stack, the contents of register bank and imf are also saved. example: correspondence between vector table address for inttbt and the entry address of the interrupt service program figure 3-2 vector table address and entry address tmp89ch42 page 55 ra003 0x03 0xfff4 0xfff5 vector table address 0xd2 0x0f 0xd203 0xd204 vector table address 0x06
a maskable interrupt is not accepted until the imf is set to 1 even if the maskable interrupt is requested in the interrupt service routine. in order to utilize nested interrupt service, the imf must be set to 1 in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to 1. as for non-maskable interrupt, keep interrupt service shorter compared with length between interrupt requests. 3.5.3 saving/restoring general-purpose registers during interrupt acceptance processing, the program counter (pc) and the program status word (psw, includes imf) are automatically saved on the stack, but the general purpose registers are not. these registers must be saved by software if necessary. when multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. the following methods are used to save/restore the general-purpose reg- isters. 3.5.3.1 using push and pop instructions to save only a specific register, push and pop instructions are available. example :using push and pop instructions pintxx push wa ; save wa register interrupt processing pop wa ; restore wa register reti ; return figure 3-3 saving/restoring general-purpose registers tmp89ch42 3. interrupt control circuit 3.5 interrupt sequence page 56 ra003 at acceptance of an interrupt psw sp pc l pc h address (example) b-4 b-3 b-2 b-1 b psw sp pc l pc h at execution of push instruction at execution of pop instruction sp at execution of an reti instruction psw w a sp pc l pc h
3.5.3.2 using data transfer instructions to save only a specific register without nested interrupts, data transfer instructions are available. example :save/store register using data transfer instructions pintxx: ld (gsava), a ; save a register interrupt processing ld a, (gsava) ; restore a register reti ; return figure 3-4 saving/restoring general-purpose registers under interrupt processing 3.5.3.3 using a register bank to save/restore general-purpose registers in non-multiple interrupt handling, the register bank function can be used to save/restore the general- purpose registers at a time. the register bank function saves (switches) the general-purpose registers by executing a register bank manipulation instruction (such as ld rbs,1) at the beginning of an interrupt service task. it is unnecessary to re-execute the register bank manipulation instruction at the end of the interrupt service task because executing the reti instruction makes a return automatically to the register bank that was being used by the main task according to the content of the psw. note: two register banks (bank0 and bank1) are available. each bank consists of 8-bit general-purpose registers (w, a, b, c, d, e, h, and l) and 16-bit general-purpose registers (ix and iy). example :saving/restoring registers, using an instruction for transfer with data memory (with the main task using the register bank bank0) pintxx: ld rbs, 1 ; switches to the register bank bank1 interrupt processing reti ; return (makes a return automatically to bank0 that was being used by the main task when the psw is restored) tmp89ch42 page 57 ra003 main task interrupt acceptance interrupt service task saving registers restoring registers interrupt return
figure 3-5 saving/restoring general-purpose registers under interrupt processing 3.5.4 interrupt return interrupt return instructions [reti]/[retn] perform as follows. [reti]/[retn] interrupt return 1. program counter (pc) and program status word (register bank) are re- stored from tha stack. 2. stack pointer (sp) is incremented by 3. tmp89ch42 3. interrupt control circuit 3.5 interrupt sequence page 58 ra003 main task interrupt service task interrupt acceptance interrupt return switching occurs to the register bank bank1. a return is made automatically to the register bank bank0. ld (rbs),1 the register bank bank0 is in use.
3.6 software interrupt (intsw) executing the swi instruction generates a software interrupt and immediately starts interrupt processing (intsw is the top-priority interrupt). use the swi instruction only for address error detection or for debugging described below. 3.6.1 address error detection 0xff is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address. code 0xff is an swi instruction, so a software interrupt is generated and an address error is detected. the address error detection range can be further expanded by writing 0xff to unused areas in the program memory. 3.6.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 3.7 undefined instruction interrupt (intundef) when the cpu tries to fetch and execute an instruction that is not defined, intundef is generated and starts the interrupt processing. intundef is accepted even if another non-maskable interrupt is in process. the current process is discontinued and the intundef interrupt process starts soon after it is requested. note: the undefined instruction interrupt (intundef) forces the cpu to jump into the interrupt vector address, as software interrupt (swi) does. tmp89ch42 page 59 ra003
3.8 revision history rev description ra003 revised from wdtcr1 to wdctr added chapter "3.5 interrupt sequence" "figure 3-3 saving/restoring general-purpose registers" revised sp position tmp89ch42 3. interrupt control circuit 3.8 revision history page 60 ra003
4. external interrupt control circuit external interrupts detects the change of the input signal and generates an interrupt request. noise can be removed by the built-in digital noise canceller. 4.1 configuration the external interrupt control circuit consists of a noise canceller, an edge detection circuit, a level detection circuit and an interrupt signal generation circuit. externally input signals are input to the rising edge or falling edge or level detection circuit for each external interrupt, after noise is removed by the noise canceller. figure 4-1 external interrupts 0/5 figure 4-2 external interrupts 1/2/3 figure 4-3 external interrupt 4 4.2 control external interrupts are controlled by the following registers: tmp89ch42 page 61 ra000 noise canceller 3 4 2 1 fcgck int4 pin int4lvl int4es int4 interrupt request abcd s z rising edge detection circuit interrupt request signal generation circuit level detection circuit falling edge detection circuit eintcr4 fs noise canceller 3 4 2 1 fcgck fs/4 inti pin intilvl inties inti interrupt request i=1 to 3 abcd s z rising edge detection circuit interrupt request signal generation circuit falling edge detection circuit eintcri noise canceller intj pin fs/4 fcgck intj interrupt request j=0,5 falling edge detection circuit interrupt request signal generation circuit
low power consumption register 3 poffcr3 7 6 5 4 3 2 1 0 (0x0f77) bit symbol - - int5en int4en int3en int2en int1en int0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 int5en int5 control 0 1 disable enable int4en int4 control 0 1 disable enable int3en int3 control 0 1 disable enable int2en int2 control 0 1 disable enable int1en int1 control 0 1 disable enable int0en int0 control 0 1 disable enable note 1: clearing intxen(x=0 to 5) to "0" stops the clock supply to the external interrupts. this invalidates the data written in the control register for each external interrupt. when using the external interrupts, set intxen to "1" and then write data into the control register for each external interrupt. note 2: interrupt request signals may be generated when intxen is changed. before changing intxen, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: bits 7 and 6 of poffset3 are read as "0". external interrupt control register 1 eintcr1 (0x0fd8) 7 6 5 4 3 2 1 0 bit symbol - - - int1lvl int1es int1nc read/write r r r r r/w r/w after reset 0 0 0 0 0 0 ini1lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 1 0 : 1 : initial state or signal level "l" signal level "h" int1es selects the interrupt request gener- ating condition for external interrupt 1 00 : an interrupt request is generated at the rising edge of the noise canceller pass signal 01 : an interrupt request is generated at the falling edge of the noise canceller pass signal 10 : an interrupt request is generated at both edges of the noise canceller pass signal 11 : reserved int1nc sets the noise canceller sampling in- terval for external interrupt 1 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz] note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. tmp89ch42 4. external interrupt control circuit 4.2 control page 62 ra000
note 3: interrupt requests may be generated when eintcr1 is changed. before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from nor- mal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/ fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: bits 7 to 5 of eintcr1 are read as "0". external interrupt control register 2 eintcr1 (0x0fd9) 7 6 5 4 3 2 1 0 bit symbol - - - int2lvl int2es int2nc read/write r r r r r/w r/w after reset 0 0 0 0 0 0 ini2lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 2 0 : 1 : initial state or signal level "l" signal level "h" int2es selects the interrupt request gener- ating condition for external interrupt 2 00 : an interrupt request is generated at the rising edge of the noise canceller pass signal 01 : an interrupt request is generated at the falling edge of the noise canceller pass signal 10 : an interrupt request is generated at both edges of the noise canceller pass signal 11 : reserved int2nc sets the noise canceller sampling in- terval for external interrupt 2 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz] note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr2 is changed. before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from nor- mal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/ fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: bits 7 to 5 of eintcr2 are read as "0". tmp89ch42 page 63 ra000
external interrupt control register 3 eintcr3 (0x0fda) 7 6 5 4 3 2 1 0 bit symbol - - - int3lvl int3es int3nc read/write r r r r r/w r/w after reset 0 0 0 0 0 0 ini3lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 3 0 : 1 : initial state or signal level "l" signal level "h" int3es selects the interrupt request gener- ating condition for external interrupt 3 00 : an interrupt request is generated at the rising edge of the noise canceller pass signal 01 : an interrupt request is generated at the falling edge of the noise canceller pass signal 10 : an interrupt request is generated at both edges of the noise canceller pass signal 11 : reserved int3nc sets the noise canceller sampling in- terval for external interrupt 3 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz] note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr3 is changed. before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from nor- mal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/ fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: bits 7 to 5 of eintcr3 are read as "0". tmp89ch42 4. external interrupt control circuit 4.2 control page 64 ra000
external interrupt control register 4 eintcr4 (0x0fdb) 7 6 5 4 3 2 1 0 bit symbol - - - int4lvl int4es int4nc read/write r r r r r/w r/w after reset 0 0 0 0 0 0 ini4lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 4 0 : 1 : initial state or signal level "l" signal level "h" int4es selects the interrupt request gener- ating condition for external interrupt 4 00 : an interrupt request is generated at the rising edge of the noise canceller pass signal 01 : an interrupt request is generated at the falling edge of the noise canceller pass signal 10 : an interrupt request is generated at both edges of the noise canceller pass signal 11 : an interrupt request is generated at "h" of the noise canceller pass signal int4nc sets the noise canceller sampling in- terval for external interrupt 4 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz] note 1: fcgck: gear clock [hz], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr4 is changed. before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from nor- mal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/ fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: the contents of eintcrx are updated each time an interrupt request signal is generated. note 5: bits 7 to 5 of eintcr4 are read as "0". 4.3 function the condition for generating interrupt request signals and the noise cancel time can be set for external interrupts 1 to 4. the condition for generating interrupt request signals and the noise cancel time are fixed for external interrupts 0 and 5. tmp89ch42 page 65 ra000
table 4-1 external interrupts source pin enable conditions interrupt request sig- nal generated at external interrupt pin input signal width and noise removal normal1/2, idle1/2 slow1/2, sleep1 int0 int0 imf and ef16 = 1 falling edge less than 1/fcgck: noise more than 1/fcgck and less than 2/fcgck: indeterminate more than 2/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int1 int1 imf and ef17 = 1 falling edge rising edge both edges less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int2 int2 imf and ef18 = 1 falling edge rising edge both edges less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int3 int3 imf and ef19 = 1 falling edge rising edge both edges less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int4 int4 imf and ef20 = 1 falling edge rising edge both edges "h" level less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int5 int5 imf and ef8 = 1 falling edge less than 1/fcgck: noise more than 1/fcgck and less than 2/fcgck: indeterminate more than 2/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal note 1: fcgck, gear clock [hz]; fs, low frequency clock [hz]; fspl, sampling interval [hz] 4.3.1 low power consumption function external interrupts have a function that saves power by using the low power consumption register (poffcr3) when they are not used. setting poffcr 3 to "0" stops (disables) the basic clock for external interrupts and helps save power. note that this makes external interrupts unavailable. setting poffcr3 to "1" supplies (ena- bles) the basic clock for external interrupts and makes external interrupts available. after reset, poffcr 3 is initialized to "0" and external interrupts become unavailable. when using the external interrupt function for the first time, be sure to set poffcr 3 to "1" in the initial setting of software (before operating the external interrupt control registers). note: interrupt request signals may be generated when intxen is changed. before changing intxen, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the oper- ation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. 4.3.2 external interrupt 0 external interrupt 0 detects the falling edge of the int0 pin and generates interrupt request signals. in normal1/2 or idle1/2 mode, pulses of less than 1/fcgck are removed as noise and pulses of 2/fcgck or more are recognized as signals. in slow/sleep mode, pulses of less than 4/fs are removed as noise and pulses of 8/fs or more are recognized as signals. tmp89ch42 4. external interrupt control circuit 4.3 function page 66 ra000
4.3.3 external interrupts 1/2/3 external interrupts 1/2/3 detect the falling edge, the rising edge or both edges of the int1, int2 and int3 pins and generate interrupt request signals. 4.3.3.1 interrupt request signal generating condition detection function select interrupt request signal generating conditions at eintcrx for external interrupts 1/2/3. table 4-2 selection of interrupt request generation edge eintcrx detected at 00 rising edge 01 falling edge 10 both edges 11 reserved note:x=1 to 3 4.3.3.2 a noise canceller pass signal monitoring function when interrupt request signals are generated the level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using eintcrx. when both edges are selected as detection edges, the edge where an interrupt is generated can be detected by reading eintcrx. note:the contents of eintcrx are updated each time an interrupt request signal is generated. figure 4-4 interrupt request generation and eintcrx 4.3.3.3 noise cancel time selection function in normal1/2 or idle1/2 mode, a signal that has been sampled by fcgck is sampled at the sampling interval selected at eintcrx. if the same level is detected three consecutive times, the signal is recognized as a signal. if not, the signal is removed as noise. tmp89ch42 page 67 ra000 signal that has passed through the noise canceller inti pin interrupt request signal (detected at the falling edge) interrupt request signal (detected at the rising edge) interrupt request signal (detected at both edges) int lvl int lvl int lvl
table 4-3 noise canceller sampling lock eintcrx sampling interval 00 fcgck 01 fcgck/2 2 10 fcgck/2 3 11 fcgck/2 4 figure 4-5 noise cancel operation in slow1/2 or sleep1 mode, a signal is sampled by the low frequency clock divided by 4. if the same level is detected twice consecutively, the signal is recognized as a signal. in idle0, sleep0 or stop mode, the noise canceller sampling operation is stopped and an external interrupts are unavailable. when operation returns to normal1/2, idle1/2, slow1/2 or sleep1 mode, sampling operation restarts. note 1: if noise is input consecutively during sampling of external interrupt pins, the noise cancel function does not work properly. set eintcrx according to the cycle of externally input noise. note 2: if an external interrupt pin is used as an output port, the input signal to the port is fixed to "l" when the mode is switched to the output mode, and thus an interrupt request occurs. to use the pin as an output port, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. note 3: interrupt requests may be generated during transition of the operation mode. before changing the op- eration mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. 4.3.4 external interrupt 4 external interrupt 4 detects the falling edge, the rising edge, both edges or "h" level of the int4 pin and generates interrupt request signals. 4.3.4.1 interrupt request signal generating condition detection function select an interrupt request signal generating condition at eintcr4 for external interrupt 4. table 4-4 selection of interrupt request generation edge eintcr4 detected at 00 rising edge 01 falling edge 10 both edges 11 "h" level interrupt tmp89ch42 4. external interrupt control circuit 4.3 function page 68 ra000 inti pin signal after noise removal i=1 to 3 noise signal
4.3.4.2 a noise canceller pass signal monitoring function when interrupt request signals are generated the level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using eintcr4. when both edges are selected as detection edges, the edge where an interrupt is generated can be detected by reading eintcr4. figure 4-6 interrupt request generation and eintcr4 4.3.4.3 noise cancel time selection function in normal1/2 or idle1/2 mode, a signal that has been sampled by fcgck is sampled at the sampling interval selected at eintcrx. if the same level is detected three consecutive times, the signal is recognized as a signal. if not, the signal is removed as noise. table 4-5 noise canceller sampling lock eintcr4 sampling interval 00 fcgck 01 fcgck/2 2 10 fcgck/2 3 11 fcgck/2 4 tmp89ch42 page 69 ra000 int4 pin interrupt request signal (detected at the falling edge) interrupt request signal (detected at the rising edge) interrupt request signal (detected at both edges) int4lvl int4lvl int4lvl int4lvl interrupt request signal (level detection) signal that has passed through the noise canceller
figure 4-7 noise cancel operation in slow1/2 or sleep1 mode, a signal is sampled by the low frequency clock divided by 4. if the same level is detected twice consecutively, the signal is recognized as a signal. in idle0, sleep0 or stop mode, the noise canceller sampling operation is stopped and an external interrupts are unavailable. when operation returns to normal1/2, idle1/2, slow1/2 or sleep1 mode, sampling operation restarts. note 1: when noise is input consecutively during sampling external interrupt pins, the noise cancel function does not work properly. set eintcrx according to the cycle of externally input noise. note 2: when an external interrupt pin is used as an output port, the input signal to the port is fixed to "l" when the mode is switched to the output mode, and thus an interrupt request occurs. to use the pin as an output port, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. note 3: interrupt requests may be generated during transition of the operation mode. before changing the op- eration mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. 4.3.5 external interrupt 5 external interrupt 5 detects the falling edge of the int5 pin and generates interrupt request signals. in normal1/2 or idle1/2 mode, pulses of less than 1/fcgck are removed as noise and pulses of 2/fcgck or more are recognized as signals. in slow/sleep mode, pulses of less than 4/fs are removed as noise and pulses of 8/fs or more are recognized as signals. tmp89ch42 4. external interrupt control circuit 4.3 function page 70 ra000 int4 pin signal after noise removal noise signal
5. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidly the cpu malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the cpu to a system recovery routine. the watchdog timer signals used for detecting malfunctions can be programmed as watchdog interrupt request signals or watchdog timer reset signals. note: care must be taken in system designing since the watchdog timer may not fulfill its functions due to disturbing noise and other effects. 5.1 configuration figure 5-1 watchdog timer configuration tmp89ch42 page 71 ra000 source clock watchdog timer interrupt requestl cpu/peripheral circuits reset fcgck/2 10 or fs/2 3 fcgck/2 12 or fs/2 5 fcgck/2 14 or fs/2 7 fcgck/2 16 or fs/2 9 watchdog timer reset signal 2 8 wdctr wdcdr wdcnt wdst overflow clear 2 3 4 6 7 8 5 control code decoder disable control circuit disable code (0xb1) clear code (0x4e) n e t d w w t d w t t d w t u o t d w t s t d w 1 t s t n i w 2 t s t n i w clear time control circuit 8-bit up counter interrupt request/reset signal control circuit r o t c e l e s
5.2 control the watchdog timer is controlled by the watchdog timer control register (wdctr), the watchdog timer control code register (wdcdr), the watchdog timer counter monitor (wdcnt) and the watchdog timer status (wdst). the watchdog timer is enabled automatically just after the warm-up operation that follows reset is finished. watchdog timer control register wdctr (0x0fd4) 7 6 5 4 3 2 1 0 bit symbol - - wdten wdtw wdtt wdtout read/write r r r/w r/w r/w r/w after reset 1 0 1 0 0 1 1 0 wdten enables/disables the watchdog tim- er operation. 0 : 1 : disable enable wdtw sets the clear time of the 8-bit up counter. 00 : the 8-bit up counter is cleared by writing the clear code at any point within the overflow time of the 8-bit up counter. 01 : a watchdog timer interrupt request is generated by writing the clear code at a point within the first quarter of the overflow time of the 8-bit up counter. the 8-bit up counter is cleared by writing the clear code after the first quarter of the overflow time has elapsed. 10 : a watchdog timer interrupt request is generated by writing the clear code at a point within the first half of the overflow time of the 8-bit up counter. the 8-bit up counter is cleared by writing the clear code after the first half of the overflow time has elapsed. 11 : a watchdog timer interrupt request is generated by writing the clear code at a point within the first three quarters of the overflow time of the 8-bit up counter. the 8-bit up counter is cleared by writing the clear code after the first three quarters of the overflow time have elapsed. wdtt sets the overflow time of the 8-bit up counter. normal mode slow mode dv9ck=0 dv9ck=1 00 : 2 18 /fcgck 2 11 /fs 2 11 /fs 01: 2 20/ fcgck 2 13 /fs 2 13 /fs 10: 2 22 /fcgck 2 15 /fs 2 15 /fs 11: 2 24 /fcgck 2 17 /fs 2 17 /fs wdtout selects an overflow detection signal of the 8-bit up counter. 0 : 1 : watchdog timer interrupt request signal watchdog timer reset request signal note 1: fcgck, gear clock [hz]; fs, low frequency clock [hz] note 2: wdctr, wdctr and wdctr cannot be changed when wdctr is "1". if wdctr is "1", clear wdctr to "0" and write the disable code (0xb1) into wdcdr to disable the watchdog timer operation. note that wdctr, wdctr and wdctr can be changed at the same time as setting wdctr to "1". note 3: bit 7 and bit 6 of wdctr are read as "1" and "0" respectively. watchdog timer control code register wdcdr (0x0fd5) 7 6 5 4 3 2 1 0 bit symbol wdtcr2 read/write w after reset 0 0 0 0 0 0 0 0 wdtcr2 writes watchdog timer control co- des. 0x4e : clears the watchdog timer. (clear code) 0xb1 : disables the watchdog timer operation and clears the 8-bit up counter when wdctr is "0". (disable code) others : invalid tmp89ch42 5. watchdog timer (wdt) 5.2 control page 72 ra000
note: wdcdr is a write-only register and must not be accessed by using a read-modify-write instruction, such as a bit operation. 8-bit up counter monitor wdcnt (0x0fd6) 7 6 5 4 3 2 1 0 bit symbol wdcnt read/write r after reset 0 0 0 0 0 0 0 0 wdcnt monitors the count value of the 8-bit up counter the count value of the 8-bit up counter is read. watchdog timer status wdst (0x0fd7) 7 6 5 4 3 2 1 0 bit symbol - - - - - wintst2 wintst1 wdtst read/write r r r r r r r r after reset 0 1 0 1 1 0 0 1 wintst2 watchdog timer interrupt request signal factor status 2 0 : no watchdog timer interrupt request signal has occurred. 1 : a watchdog timer interrupt request signal has occurred due to the overflow of the 8-bit up counter. wintst1 watchdog timer interrupt request signal factor status 1 0 : no watchdog timer interrupt request signal has occurred. 1 : a watchdog timer interrupt request signal has occurred due to releasing of the 8-bit up counter outside the clear time. wdtst watchdog timer operating state sta- tus 0 : 1 : operation disabled operation enabled note 1: wdst and wdst are cleared to "0" by reading wdst. note 2: values after reset are read from bits 7 to 3 of wdst. tmp89ch42 page 73 ra000
5.3 functions the watchdog timer can detect the cpu malfunctions and deadlock by detecting the overflow of the 8-bit up counter and detecting releasing of the 8-bit up counter outside the clear time. the watchdog timer stoppage and other abnormalities can be detected by reading the count value of the 8-bit up counter at random times and comparing the value to the last read value. 5.3.1 setting of enabling/disabling the watchdog timer operation setting wdctr to "1" enables the watchdog timer operation, and the 8-bit up counter starts counting the source clock. wdctr is initialized to "1" after the warm-up operation that follows reset is released. this means that the watchdog timer is enabled. to disable the watchdog timer operation, clear wdctr to "0" and write 0xb1 into wdcdr. disabling the watchdog timer operation clears the 8-bit up counter to "0". note: if the overflow of the 8-bit up counter occurs at the same time as 0xb1 (disable code) is written into wdcdr with wdctr set at "1", the watchdog timer operation is disabled preferentially and the overflow detection is not executed. to re-enable the watchdog timer operation, set wdctr to "1". there is no need to write a control code into wdcdr. figure 5-2 wdctr set timing and overflow time note: the 8-bit up counter source clock operates out of synchronization with wdctr. therefore, the first overflow time of the 8-bit up counter after wdctr is set to "1" may get shorter by a maximum of 1 source clock. the 8-bit up counter must be cleared within the period of the overflow time minus 1 source clock cycle. 5.3.2 setting the clear time of the 8-bit up counter wdctr sets the clear time of the 8-bit up counter. when wdctr is "00", the clear time is equal to the overflow time of the 8-bit up counter, and the 8-bit up counter can be cleared at any time. when wdctr is not "00", the clear time is fixed to only a certain period within the overflow time of the 8-bit up counter. if the operation for releasing the 8-bit up counter is attempted outside the clear time, a watchdog timer interrupt request signal occurs. at this time, the watchdog timer is not cleared but continues counting. if the 8-bit up counter is not cleared within the clear time, a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs due to the overflow, depending on the wdctr setting. tmp89ch42 5. watchdog timer (wdt) 5.3 functions page 74 ra000 wdctr 0x00 0x01 0xff wdctr 0x00 watchdog timer source clock 8-bit up counter value interrupt request signal 1 clock (max.) overflow time overflow time
figure 5-3 wdctr and the 8-bit up counter clear time 5.3.3 setting the overflow time of the 8-bit up counter wdctr sets the overflow time of the 8-bit up counter. when the 8-bit up counter overflows, a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs, depending on the wdctr setting. if the watchdog timer interrupt request signal is selected as the malfunction detection signal, the watchdog counter continues counting, even after the overflow has occurred. the watchdog timer temporarily stops counting up in the stop mode (including warm-up) or in the idle/ sleep mode, and restarts counting up after the stop/idle/sleep mode is released. to prevent the 8-bit up counter from overflowing immediately after the stop/idle/sleep mode is released, it is recommended to clear the 8-bit up counter before the operation mode is changed. table 5-1 watchdog timer overflow time (fcgck=10.0 mhz; fs=32.768 khz) wdtt watchdog timer overflow time [s] normal mode slow mode dv9ck = 0 dv9ck = 1 00 26.21 m 62.50 m 62.50 m 01 104.86 m 250.00 m 250.00 m 10 419.43 m 1.000 1.000 11 1.678 4.000 4.000 note: the 8-bit up counter source clock operates out of synchronization with wdctr. therefore, the first overflow time of the 8-bit up counter after wdctr is set to "1" may get shorter by a maximum of 1 source clock. the 8-bit up counter must be cleared within a period of the overflow time minus 1 source clock cycle. 5.3.4 setting an overflow detection signal of the 8-bit up counter wdctr selects a signal to be generated when the overflow of the 8-bit up counter is detected. 1. when the watchdog timer interrupt request signal is selected (when wdctr is "0") releasing wdctr to "0" causes a watchdog timer interrupt request signal to occur when the 8-bit up counter overflows. a watchdog timer interrupt is a non-maskable interrupt, and its request is always accepted, regardless of the interrupt master enable flag (imf) setting. note: when a watchdog timer interrupt is generated while another interrupt, including a watchdog timer interrupt, is already accepted, the new watchdog timer interrupt is processed immediately and the preceding interrupt is put on hold. therefore, if watchdog timer interrupts are generated continuously without execution of the retn in- struction, too many levels of nesting may cause a malfunction of the microcontroller. tmp89ch42 page 75 ra000 when wdctr is ?00? 8-bit up counter value when wdctr is ?01? when wdctr is ?10? when wdctr is ?11? 0x40 0x7f 0x80 0xbf 0xc0 0xff 0x00 0xff 0x00 0x01 0x3f clear time clear time outside the clear time clear time outside the clear time clear time outside the clear time
2. when the watchdog timer reset request signal is selected (when wdctr is "1") setting wdctr to "1" causes a watchdog timer reset request signal to occur when the 8-bit up counter overflows. this watchdog timer reset request signal resets the tmp89ch42 and starts the warm-up operation. 5.3.5 writing the watchdog timer control codes the watchdog timer control codes are written into wdcdr. by writing 0x4e (clear code) into wdcdr, the 8-bit up counter is cleared to "0" and continues counting the source clock. when wdctr is "0", writing 0xb1 (disable code) into wdcdr disables the watchdog timer operation. to prevent the 8-bit up counter from overflowing, clear the 8-bit up counter in a period shorter than the overflow time of the 8-bit up counter and within the clear time. by designing the program so that no overflow will occur, the program malfunctions and deadlock can be detected through interrupts generated by watchdog timer interrupt request signals. by applying a reset to the microcomputer using watchdog timer reset request signals, the cpu can be restored from malfunctions and deadlock. example: when wdctr is "0", set the watchdog timer detection time to 2 20 / fcgck [s], set the counter clear time to half of the overflow time, and allow a watchdog timer reset request signal to occur if a malfunction is detected. ld (wdctr), 0y00110011 ; wdtw10, wdtt01, wdtout1 clear the 8-bit up counter at a point after half of its overflow time and within a period of the overflow time minus 1 source clock cycle. ld (wdcdr), 0x4e ; clear the 8-bit up counter clear the 8-bit up counter at a point after half of its overflow time and within a period of the overflow time minus 1 source clock cycle. ld (wdcdr), 0x4e ; clear the 8-bit up counter note: if the overflow of the 8-bit up counter and writing of 0x4e (clear code) into wdcdr occur simultaneously, the 8-bit up counter is cleared preferentially and the overflow detection is not executed. 5.3.6 reading the 8-bit up counter the counter value of the 8-bit up counter can be read by reading wdcnt. the stoppage of the 8-bit up counter can be detected by reading wdcnt at random times and comparing the value to the last read value. 5.3.7 reading the watchdog timer status the watchdog timer status can be read at wdst. wdst is set to "1" when the watchdog timer operation is enabled, and it is cleared to "0" when the watchdog timer operation is disabled. wdst is set to "1" when a watchdog timer interrupt request signal occurs due to the overflow of the 8-bit up counter. tmp89ch42 5. watchdog timer (wdt) 5.3 functions page 76 ra000
wdst is set to "1" when a watchdog timer interrupt request signal occurs due to the operation for releasing the 8-bit up counter outside the clear time. you can know which factor has caused a watchdog timer interrupt request signal by reading wdst and wdst in the watchdog timer interrupt service routine. wdst and wdst are cleared to "0" when wdst is read. if wdst is read at the same time as the condition for turning wdst or wdst to "1" is satisfied, wdst or wdst is set to "1", rather than being cleared. figure 5-4 changes in the watchdog timer status tmp89ch42 page 77 ra000 8-bit up counter value when wdctr is ?10? writing of 4eh (clear code) wdst watchdog timer interrupt request signal interrupt request signal generated by clearing the 8-bit up counter outside the clear time interrupt request signal generated by the overflow of the 8-bit up counter 0x40 0x01 0x7f 0x80 0xbf 0xc0 0xff 0x00 0xff 0x00 0x01 0x3f clear time outside the clear time reading of wdst wdst
tmp89ch42 5. watchdog timer (wdt) 5.3 functions page 78 ra000
6. power-on reset circuit the power-on reset circuit generates a reset when the power is turned on. when the supply voltage is lower than the detection voltage of the power-on reset circuit, a power-on reset signal is generated. 6.1 configuration the power-on reset circuit consists of a reference voltage generation circuit and a comparator. the supply voltage divided by ladder resistor is compared with the voltage generated by the reference voltage generation circuit by the comparator. figure 6-1 power-on reset circuit 6.2 function when power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage of the power-on reset circuit, a power-on reset signal is generated and if it is higher than the releasing voltage of the power- on reset circuit, a power-on reset signal is released. when power supply voltage goes down, if the supply voltage is equal to or lower than the detecting voltage of the power-on reset circuit, a power-on reset signal is generated. until the power-on reset signal is generated, a warm-up circuit and a cpu is reset. when the power-on reset signal is released, the warm-up circuit is activated. the reset of the cpu and peripheral circuits is released after the warm-up time that follows reset release has elapsed. increase the supply voltage into the operating range during the period from detection of the power-on reset release voltage until the end of the warm-up time that follows reset release. if the supply voltage has not reached the operating range by the end of the warm-up time that follows reset release, the tmp89ch42 cannot operate properly. tmp89ch42 page 79 ra000 vdd power-on reset signal comparator reference voltage generation circuit
note 1: the power-on reset circuit may operate improperly, depending on fluctuations in the supply voltage (vdd). refer to the electrical characteristics and take them into consideration when designing equipment. note 2: for the ac timing, refer to the electrical characteristics. figure 6-2 operation timing of power-on reset tmp89ch42 6. power-on reset circuit 6.2 function page 80 ra000 supply voltage (vdd) vproff operating voltage vpron vdd ppw pron warm-up counter start pwup proff power-on reset signal warm-up counter clock cpu/peripheral circuits reset signal
7. voltage detection circuit the voltage detection circuit detects any decrease in the supply voltage and generates intvltd interrupt request signals and voltage detection reset signals. note: the voltage detection circuit may operate improperly, depending on fluctuations in the supply voltage (vdd). refer to the electrical characteristics and take them into consideration when designing equipment. 7.1 configuration the voltage detection circuit consists of a reference voltage generation circuit, a detection voltage level selection circuit, a comparator and control registers. the supply voltage (vdd) is divided by the ladder resistor and input to the detection voltage selection circuit. the detection voltage selection circuit selects a voltage according to the specified detection voltage (vdxlvl) (x = 1 or 2) , and the comparator compares it with the reference voltage. when the comparator detects the selected voltage, a voltage detection reset signal or an intvltd interrupt request signal can be generated. whether to generate a voltage detection reset signal or an intvltd interrupt request signal can be programmed by software. in the former case, a voltage detection reset signal is generated when the supply voltage (vdd) becomes lower than the detection voltage (vd x lvl). in the latter case, an intvltd interrupt request signal is generated when the supply voltage (vdd) falls to the detection voltage level. note: since the comparators used for voltage detection do not have a hysteresis structure, intvltd interrupt request signals may be generated frequently if the supply voltage (vdd) is close to the detection voltage (vdxlvl). intvltd interrupt request signals may be generated not only when the supply voltage falls to the detection voltage but also when it rises to the detection voltage. figure 7-1 voltage detection circuit tmp89ch42 page 81 rb000 vdd reference voltage generation circuit ? + ? + vd1en vd1mod vd2en vd2mod vd2lvl vd1lvl vd1sf vd1f vd2sf vd2f vdcr2 detection voltage 1 level selection circuit detection voltage 2 level selection circuit vdcr1 voltage detection reset signal 1 voltage detection reset signal 2 intvltd interrupt request signal f/f f/f interrupt request signal generation circuit internal bus
7.2 control the voltage detection circuit is controlled by voltage detection control registers 1 and 2. voltage detection control register 1 vdcr1 (0x0fc6) 7 6 5 4 3 2 1 0 bit symbol vd2f vd2sf vd2lvl vd1f vd1sf vd1lvl read/write r/w read only r/w r/w read only r/w after reset 0 0 1 0 0 0 0 0 vd2f voltage detection 2 flag (retains the state when vdd 7.3 function two detection voltages (vdxlvl, x = 1 to 2) can be set in the voltage detection circuit. for each voltage, e nabling/ disabling the voltage detection and the operation to be executed when the supply voltage (vdd) falls to or below the detection voltage (vdxlvl) can be programmed. 7.3.1 enabling/disabling the voltage detection operation setting vdcr2 to "1" enables the voltage detection operation. setting it to "0" disables the oper- ation. vdcr2 is cleared to "0" immediately after a power-on reset or a reset by an external reset input is released. note: when the supply voltage (vdd) is lower than the detection voltage (vd x lvl), setting vdcr2 to "1" generates an intvltd interrupt request signal or a voltage detection reset signal at the time. 7.3.2 selecting the voltage detection operation mode when vdcr2 is set to "0", the voltage detection operation mode is set to generate intvltd interrupt request signals. when vdcr2 is set to "1", the operation mode is set to generate voltage detection reset signals. ? when the operation mode is set to generate intvltd interrupt signals (vdcr2="0") when vdcr2="1", an intvltd interrupt request signal is generated when the supply voltage (vdd) falls to the detection voltage (vdxlvl). figure 7-2 voltage detection interrupt request note1: since the comparators used for voltage detection do not have a hysteresis structure, intvltd interrupt request signals may be generated frequently when the supply voltage (vdd) is close to the detection voltage (vdxlvl). intvltd interrupt request signals may be generated not only when the supply voltage falls to the detection voltage but also when it rises to the detection voltage. note2: in debug using the rte870/c1 in-circuit emulator (ice mode) with the tmp89c900 mounted on it, no interrupt is generated when the supply voltage rises to the detection voltage. since the #!undefined!# may operate differently, take account of this difference when debugging programs. note3: if the supply voltage (vdd) falls to the detection voltage (vdxlvl) during idle0 or sleep0 mode, an intvltd interrupt request signal is generated after the tbt counts the specified period and idle0 or sleep mode is released. in the case of stop mode, an intlvtd interrupt request signal is generated after stop mode is released by the stop pin. ? when the operation mode is set to generate voltage detection reset signals (vdcr2="1") when vdcr2 = "1", a voltage detection reset signal is generated when the supply voltage (vdd) becomes lower than the detection voltage (vdxlvl). tmp89ch42 page 83 rb000 detection voltage level vdd level intvltd interruptrequest signal (note1) vdcr2 (note1,2)
vdcr1 and vdcr2 are initialized by a power-on reset or an external reset input only. a voltage detection reset signal is generated continuously as long as the supply voltage (vdd) is lower than the detection voltage (vdxlvl). figure 7-3 voltage detection reset signal 7.3.3 selecting the detection voltage level select a detection voltage at vdcr1. 7.3.4 voltage detection flag and voltage detection status flag the magnitude relation between the supply voltage (vdd) and the detection voltage (vd x lvl) can be checked by reading vdcr1 and vdcr1. if vdcr2 is set at "1", when the supply voltage (vdd) becomes lower than the detection voltage (vdxlvl), vdcr1 is set to "1" and is held in this state. vdcr1 is not cleared to "0" when the supply voltage (vdd) becomes equal to or higher than the detection voltage (vdxlvl). when vdcr2 is cleared to "0" after vdcr1 is set to "1", the previous state is still held. to clear vdcr1, "0" must be written to it. if vdcr2 is set at "1", when the supply voltage (vdd) becomes lower than the detection voltage (vdxlvl), vdcr1 is set to "1". when the supply voltage (vdd) becomes equal to or higher than the detection voltage (vdxlvl), vdcr1 is cleared to "0". unlike vdcr1, vdcr1 does not hold the set state. note 1: when the supply voltage (vdd) becomes lower than the detection voltage (vd x lvl) in the stop, idle0 or sleep0 mode, the voltage detection flag and the voltage detection status flag are changed after the oper- ation mode is returned to normal or slow mode. note 2: depending on the voltage detection timing, the voltage detection status flag (vd x sf) may be changed earlier than the voltage detection flag (vdxf) by a maximum of 2/fcgck[s]. tmp89ch42 7. voltage detection circuit 7.3 function page 84 rb000 detection voltage level vdd level voltage detection reset signal vdcr2
figure 7-4 changes in the voltage detection flag and the voltage detection status flag tmp89ch42 page 85 rb000 detection voltage level vdd level vdcr2 vdcr1 vdcr1 write "0" to vdcr1 the flag is not set because vdcr2 is "0"
7.4 register settings 7.4.1 setting procedure when the operation mode is set to generate intvltd interrupt request signals when the operation mode is set to generate intvltd interrupt request signal, make the following setting: 1. clear the voltage detection circuit interrupt enable flag to "0". 2. set the detection voltage at vdcr1(x=1 to 2). 3. clear vdcr2 to "0" to set the operation mode to generate intvltd interrupt request signals. 4. set vdcr2 to "1" to enable the voltage detection operation. 5. wait for 5 [s] or more until the voltage detection circuit becomes stable. 6. make sure that vdcr1 is "0". 7. clear the voltage detection circuit interrupt latch to "0" and set the interrupt enable flag to "1" to enable interrupts. note: when the supply voltage (vdd) is close to the detection voltage (vdxlvl), voltage detection request signals may be generated frequently. if this may pose any problem, execute appropriate wait processing depending on fluctuations in the system power supply and clear the interrupt latch before returning from the intvltd interrupt service routine. to disable the voltage detection circuit while it is enabled with the intvltd interrupt request, make the following setting: 1. clear the voltage detection circuit interrupt enable flag to "0". 2. clear vdcr2 to "0" to disable the voltage detection operation. note: if the voltage detection circuit is disabled without clearing interrupt enable flag, unexpected interrupt request may occur. 7.4.2 setting procedure when the operation mode is set to generate voltage detection reset signals when the operation mode is set to generate voltage detection reset signals, make the following setting: 1. clear the voltage detection circuit interrupt enable flag to "0". 2. set the detection voltage at vdcr1(x=1 to 2). 3. clear vdcr2 to "0" to set the operation mode to generate intvltd interrupt request signals. 4. set vdcr2 to "1" to enable the voltage detection operation. 5. wait for 5 [s] or more until the voltage detection circuit becomes stable. 6. make sure that vdcr1 is "0". 7. clear vdcr1 to "0". 8. set vdcr2 to "1" to set the operation mode to generate voltage detection reset signals. note 1: vdcr1 and vdcr2 are initialized by a power-on reset or an external reset input only. if the supply voltage (vdd) becomes lower than the detection voltage (vd x lvl) in the period from release of the voltage detection reset until clearing of vdcr2 to "0", a voltage detection reset signal is generated immediately. note 2: the voltage detection reset signals are generated continuously as long as the supply voltage (vdd) is lower than the detection voltage (vdxlvl). to disable the voltage detection circuit while it is enabled with the voltage detection reset, make the following setting: 1. clear the voltage detection circuit interrupt enable flag to "0". tmp89ch42 7. voltage detection circuit 7.4 register settings page 86 rb000
2. clear vdcr2 to "0" to set the operation mode to generate intvltd interrupt request signals. 3. clear vdcr2 to "0" to disable the voltage detection operation. note: if the voltage detection circuit is disabled without clearing interrupt enable flag, unexpected interrupt request may occur. tmp89ch42 page 87 rb000
7.5 revision history rev description ra001 " voltage detection control register 1" revised vd1lvl and vd2lvl. ra002 revised from vdcr2 to vdcr1 ra003 "7.4.1 setting procedure when the operation mode is set to generate intvltd interrupt request signals" added description to disable the voltage detection circuit. "7.4.2 setting procedure when the operation mode is set to generate voltage detection reset signals" added description to disable the voltage detection circuit. added step 7. " voltage detection control register 2" added note 3. "7.3.5 selecting the stop mode release signal" added note 4. ra004 revised "voltage detection interrupt" to "intvltd interrupt". revised initial value of vdcr1 "00" to "10". rb000 deleted vdcr2 function. added note of intvltd interrupt. "7.3.2 selecting the voltage detection operation mode" revised description. tmp89ch42 7. voltage detection circuit 7.5 revision history page 88 rb000
8. i/o ports the tmp89ch42 has 8 parallel input/output ports (40 pins) as follows: table 8-1 list of i/o ports port name pin name number of pins input/output secondary functions port p0 p03 to p00 (note) 4 (note) input/output also used as the high-frequency oscillator connection pin and the low- frequency oscillator connection pin port p1 p13 to p10 4 input/output also used as the external reset input, the external interrupt input and the stop mode release signal input port p2 p27 to p20 8 input/output also used as the uart input/output, the serial interface input/output and the serial bus interface input/output port p4 p47 to p40 8 input/output also used as the analog input and the key-on wakeup input port p7 p77 to p70 8 input/output also used as the timer counter input/output, the divider output and the external interrupt input port p8 p81 to p80 2 input/output also used as the timer counter input/output port p9 p91 to p90 2 input/output also used as the uart input/output port pb pb7 to pb4 4 input/output also used as the uart input/output and the serial interface input/out- put note: p00 and p01 pins can not be used for the i/o port, because they should be connected with the high frequency osc input. tmp89ch42 page 89 ra007
each output port contains a latch, which holds the output data. no input port has a latch, so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing. figure 8-1 shows input/output timing examples. external data is read from an i/o port in the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. data is output to an i/o port in the next cycle of the write cycle during execution of the write instruction. figure 8-1 input/output timing (example) note:the positions of the read and write cycles may vary, depending on the instruction. tmp89ch42 8. i/o ports page 90 ra007 instruction execution cycle system clock internal read signal data input example: ld a, (x) fetch cycle fetch cycle read cycle instruction execution cycle internal write signal data output example: ld (x), a fetch cycle fetch cycle (a) input timing write cycle (b) output timing system clock
8.1 i/o port control registers the following control registers are used for i/o ports. (the port number is indicated in place of x.) registers that can be set vary depending on the port. for details, refer to the description of each port. ? pxdr register this is the register for setting output data. when a port is set to the "output mode", the value specified at pxdr is output from the port. ? pxprd register this is the register for reading input data. when a port is set to the "input mode", the current port input status can be read by reading pxprd. ? pxcr register this register switches a port between input and output. a port can be switched between the "input mode" and the "output mode". ? pxfc register this register enables the secondary function output of each port. the secondary function output of each port can be enabled or disabled. ? pxoutcr register this register switches the port output between the c-mos output and the open drain output. ? pxpu register this register determines whether or not the built-in pull-up resistor is connected when a port is used in the input mode or as the open drain output. tmp89ch42 page 91 ra007
8.2 list of i/o port settings for the setting methods for individual i/o ports, refer to the following table. table 8-2 list of i/o port settings port name pin name function register set value pxcr pxoutcr pxfc other required settings port p0 p03 to p00 port input 0 without register 0 port output 1 0 p03 xtout * without register p02 xtin * 1 p01 xout * without register p00 xin * 1 port p1 p13 to p11 port input 0 without register without register port output 1 p10 port input 0 note 1 p10 port output 1 note 1 p13 int1 input 0 p12 int0 input 0 p11 int5 input 0 p11 stop input 0 p10 reset input * note 1 port p2 p27 to p20 port input 0 * * port output 1 ** 0 p25 sclk0 input 0 * * sersel="01" sclk0 output 1 ** 1 sersel="01" p24 scl0 input/output 1 without register 1 sersel="*0" si input 0 * sersel="01" p23 sda0 input/output 1 without register 1 sersel="*0" so output 1 1 sersel="01" p22 sclk0 input 0 * * sersel

▲Up To Search▲

Price & Availability of TMP89CH42UG

	To Download TMP89CH42UG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .